soc/intel/baytrail: Use non-evict CAR setup
The CAR setup is almost identical to the cpu/intel/non-evict CAR setup, with the only difference that L2 cache needs to be separately enabled. Currently this assumes that it is possible to use a static Kconfig option to cover all CPU's requiring this. Change-Id: Iae9b584bc0d32a56be2e6e2b2e893897eb448aa5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Arthur Heymans
Patrick Georgi
parent
c9e33573c1
commit
b1c57d1beb
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@ -40,6 +40,7 @@ config CPU_SPECIFIC_OPTIONS
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select POSTCAR_STAGE
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select POSTCAR_CONSOLE
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select CPU_INTEL_COMMON
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select CPU_HAS_L2_ENABLE_MSR
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config VBOOT
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select VBOOT_STARTS_IN_ROMSTAGE
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@ -1,4 +1,4 @@
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cpu_incs-y += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
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cpu_incs-y += $(obj)/fmap_config.h
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romstage-y += romstage.c
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romstage-y += raminit.c
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@ -1,217 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2007-2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/post_code.h>
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#include <cpu/x86/msr.h>
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#include "fmap_config.h"
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/* The full cache-as-ram size includes the cache-as-ram portion from coreboot
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* and the space used by the reference code. These 2 values combined should
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* be a power of 2 because the MTRR setup assumes that. */
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#define CACHE_AS_RAM_SIZE \
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(CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE)
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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/* Cache all of CBFS just below 4GiB as Write-Protect type. */
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#define CODE_CACHE_SIZE _ALIGN_UP_POW2(___FMAP__COREBOOT_SIZE)
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#define CODE_CACHE_BASE (-CODE_CACHE_SIZE)
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#define CODE_CACHE_MASK (~(CODE_CACHE_SIZE - 1))
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#define NoEvictMod_MSR 0x2e0
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#define BBL_CR_CTL3_MSR 0x11e
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cache_as_ram:
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post_code(0x20)
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/* Send INIT IPI to all excluding ourself. */
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movl $0x000C4500, %eax
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movl $0xFEE00300, %esi
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movl %eax, (%esi)
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/* All CPUs need to be in Wait for SIPI state */
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wait_for_sipi:
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movl (%esi), %eax
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bt $12, %eax
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jc wait_for_sipi
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post_code(0x21)
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/* Configure the default memory type to uncacheable as well as disable
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* fixed and variable range mtrrs. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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andl $(~0x00000cff), %eax
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wrmsr
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post_code(0x22)
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/* Zero the variable MTRRs. */
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movl $IA32_MCG_CAP, %ecx
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rdmsr
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movzx %al, %ebx
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/* First variable MTRR. */
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movl $MTRR_PHYS_BASE(0), %ecx
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xorl %eax, %eax
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xorl %edx, %edx
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1:
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wrmsr
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inc %ecx
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dec %ebx
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jnz 1b
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/* Clear/disable fixed MTRRs */
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mov $fixed_mtrr_list_size, %ebx
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xor %eax, %eax
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xor %edx, %edx
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clear_fixed_mtrr:
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add $-2, %ebx
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movzwl fixed_mtrr_list(%ebx), %ecx
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wrmsr
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jnz clear_fixed_mtrr
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/* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */
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movl $0x80000008, %eax
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cpuid
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movb %al, %cl
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sub $32, %cl
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movl $1, %edx
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shl %cl, %edx
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subl $1, %edx
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/* Preload high word of address mask (in %edx) for Variable
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* MTRRs 0 and 1.
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*/
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addrsize_set_high:
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xorl %eax, %eax
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movl $MTRR_PHYS_MASK(0), %ecx
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wrmsr
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movl $MTRR_PHYS_MASK(1), %ecx
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wrmsr
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post_code(0x23)
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/* Set Cache-as-RAM base address. */
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movl $(MTRR_PHYS_BASE(0)), %ecx
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movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
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xorl %edx, %edx
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wrmsr
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post_code(0x24)
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/* Set Cache-as-RAM mask. */
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movl $(MTRR_PHYS_MASK(0)), %ecx
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rdmsr
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movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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wrmsr
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post_code(0x25)
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/* Set code caching up for romstage. */
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movl $(MTRR_PHYS_BASE(1)), %ecx
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movl $(CODE_CACHE_BASE | MTRR_TYPE_WRPROT), %eax
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xorl %edx, %edx
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wrmsr
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movl $MTRR_PHYS_MASK(1), %ecx
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rdmsr
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movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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wrmsr
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/* Enable MTRR. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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orl $MTRR_DEF_TYPE_EN, %eax
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wrmsr
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post_code(0x26)
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/* Enable the L2 cache. */
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movl $BBL_CR_CTL3_MSR, %ecx
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rdmsr
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orl $0x100, %eax
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wrmsr
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post_code(0x27)
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/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
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movl %cr0, %eax
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andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
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invd
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movl %eax, %cr0
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/* enable the 'no eviction' mode */
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movl $NoEvictMod_MSR, %ecx
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rdmsr
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orl $1, %eax
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wrmsr
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post_code(0x28)
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/* Clear the cache memory region. This will also fill up the cache */
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movl $CACHE_AS_RAM_BASE, %esi
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movl %esi, %edi
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movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
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xorl %eax, %eax
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rep stosl
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/* enable no evict mode */
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movl $NoEvictMod_MSR, %ecx
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rdmsr
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orl $2, %eax
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wrmsr
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post_code(0x29)
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/* Setup the stack. */
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mov $_car_stack_end, %esp
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/* Need to align stack to 16 bytes at call instruction. Account for
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the pushes below. */
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andl $0xfffffff0, %esp
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subl $4, %esp
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/* push TSC and BIST to stack */
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movd %mm0, %eax
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pushl %eax /* BIST */
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movd %mm2, %eax
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pushl %eax /* tsc[63:32] */
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movd %mm1, %eax
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pushl %eax /* tsc[31:0] */
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before_c_entry:
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post_code(0x2a)
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call bootblock_c_entry_bist
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/* Should never see this postcode */
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post_code(POST_DEAD_CODE)
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.Lhlt:
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hlt
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jmp .Lhlt
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fixed_mtrr_list:
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.word MTRR_FIX_64K_00000
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.word MTRR_FIX_16K_80000
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.word MTRR_FIX_16K_A0000
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.word MTRR_FIX_4K_C0000
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.word MTRR_FIX_4K_C8000
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.word MTRR_FIX_4K_D0000
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.word MTRR_FIX_4K_D8000
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.word MTRR_FIX_4K_E0000
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.word MTRR_FIX_4K_E8000
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.word MTRR_FIX_4K_F0000
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.word MTRR_FIX_4K_F8000
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fixed_mtrr_list_size = . - fixed_mtrr_list
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