vc/amd/fsp/picasso: Add FSP-M UPD enable_sata to 0xC7 to match FSP
BUG=b:162302027 BRANCH=zork Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Change-Id: I4b5c3b351b6232f8b0418ead47d87aaddd350668 Cq-Depend: chrome-internal:3201648 Cq-Depend: chrome-internal:3202602 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44863 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -54,7 +54,7 @@ typedef struct __packed {
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/** Offset 0x00C4**/ uint8_t aclk_dpm0_freq_400MHz;
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/** Offset 0x00C5**/ uint8_t unused5;
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/** Offset 0x00C6**/ uint8_t unused6;
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/** Offset 0x00C7**/ uint8_t unused7;
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/** Offset 0x00C7**/ uint8_t sata_enable;
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/** Offset 0x00C8**/ uint32_t tseg_size;
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/** Offset 0x00CC**/ uint8_t pspp_policy;
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/** Offset 0x00CD**/ uint8_t audio_soundwire;
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