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Braswell: Separate L1 Sub State init procedure for boards. 

Original-Reviewed-on: https://chromium-review.googlesource.com/312743
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>

Change-Id: Ib0a891f229477cf359bff6cd02f305606468f07f
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Reviewed-on: https://review.coreboot.org/12750
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kenji Chen 2015-11-16 17:08:32 +08:00 committed by Martin Roth
parent c4153c1b15
commit b1e4bd0d28
3 changed files with 2 additions and 1 deletions
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1
src/mainboard/google/cyan/Kconfig
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@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_LPC_TPM
select SOC_INTEL_BRASWELL select SOC_INTEL_BRASWELL
select HAVE_ACPI_RESUME select HAVE_ACPI_RESUME
select PCIEXP_L1_SUB_STATE
config CHROMEOS config CHROMEOS
select LID_SWITCH select LID_SWITCH

1
src/mainboard/intel/strago/Kconfig
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@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_LPC_TPM
select SOC_INTEL_BRASWELL select SOC_INTEL_BRASWELL
select PCIEXP_L1_SUB_STATE
config CHROMEOS config CHROMEOS
select LID_SWITCH select LID_SWITCH

1
src/soc/intel/braswell/Kconfig
View File

@ -28,7 +28,6 @@ config CPU_SPECIFIC_OPTIONS
select PCIEXP_ASPM select PCIEXP_ASPM
select PCIEXP_CLK_PM select PCIEXP_CLK_PM
select PCIEXP_COMMON_CLOCK select PCIEXP_COMMON_CLOCK
select PCIEXP_L1_SUB_STATE
select PLATFORM_USES_FSP1_1 select PLATFORM_USES_FSP1_1
select REG_SCRIPT select REG_SCRIPT
select SOC_INTEL_COMMON select SOC_INTEL_COMMON