Braswell: Separate L1 Sub State init procedure for boards.

Original-Reviewed-on: https://chromium-review.googlesource.com/312743
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>

Change-Id: Ib0a891f229477cf359bff6cd02f305606468f07f
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Reviewed-on: https://review.coreboot.org/12750
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/mainboard/google/cyan/Kconfig

@@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select MAINBOARD_HAS_LPC_TPM
 	select SOC_INTEL_BRASWELL
 	select HAVE_ACPI_RESUME
+	select PCIEXP_L1_SUB_STATE
 
 config CHROMEOS
 	select LID_SWITCH

src/mainboard/intel/strago/Kconfig

@@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select MAINBOARD_HAS_CHROMEOS
 	select MAINBOARD_HAS_LPC_TPM
 	select SOC_INTEL_BRASWELL
+	select PCIEXP_L1_SUB_STATE
 
 config CHROMEOS
 	select LID_SWITCH

src/soc/intel/braswell/Kconfig

@@ -28,7 +28,6 @@ config CPU_SPECIFIC_OPTIONS
 	select PCIEXP_ASPM
 	select PCIEXP_CLK_PM
 	select PCIEXP_COMMON_CLOCK
-	select PCIEXP_L1_SUB_STATE
 	select PLATFORM_USES_FSP1_1
 	select REG_SCRIPT
 	select SOC_INTEL_COMMON