riscv: use mret to invoke M-mode payload and disable interrupts
Fixes a logic error that sets MPIE, but didn't use mret to return to the payload. This left MIE set to an undefined value. Now all modes are handled the same way: - Trap vector base address point to the payload - Disable Interrupt - Return to payload using mret TEST=Run an M-mode payload Change-Id: Iaab595f916949c57104ec00f8b06ea047fe76bba Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33462 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -19,23 +19,38 @@
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#include <arch/boot.h>
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#include <arch/encoding.h>
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#include <console/console.h>
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#include <vm.h>
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void run_payload(struct prog *prog, void *fdt, int payload_mode)
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{
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void (*doit)(int hart_id, void *fdt) = prog_entry(prog);
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int hart_id = read_csr(mhartid);
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uintptr_t status = read_csr(mstatus);
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status &= ~MSTATUS_MPIE;
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status &= ~MSTATUS_MPP;
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status = INSERT_FIELD(status, MSTATUS_MPIE, 0);
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switch (payload_mode) {
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case RISCV_PAYLOAD_MODE_U:
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status = INSERT_FIELD(status, MSTATUS_MPP, PRV_U);
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/* Trap vector base address point to the payload */
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write_csr(utvec, doit);
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/* disable U-Mode interrupt */
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write_csr(uie, 0);
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break;
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case RISCV_PAYLOAD_MODE_S:
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status |= MSTATUS_SPP;
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status = INSERT_FIELD(status, MSTATUS_MPP, PRV_S);
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/* Trap vector base address point to the payload */
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write_csr(stvec, doit);
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/* disable S-Mode interrupt */
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write_csr(sie, 0);
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/* disable MMU */
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write_csr(satp, 0);
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break;
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case RISCV_PAYLOAD_MODE_M:
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doit(hart_id, fdt);
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return;
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status = INSERT_FIELD(status, MSTATUS_MPP, PRV_M);
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/* Trap vector base address point to the payload */
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write_csr(mtvec, doit);
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/* disable M-Mode interrupt */
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write_csr(mie, 0);
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break;
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default:
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die("wrong privilege level for payload");
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break;
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