From b20aac072144e650dd5ba93bb4bfce1e061732e8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Wed, 14 Oct 2020 19:30:46 +0200 Subject: [PATCH] soc/intel/skl,acpi/acpigen: convert global CPPC package to local one MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the global CPPC package \GCPC to the first logical core CP00 and adapt the reference in the other cores. This is cleaner and avoids confusion. Test: dumped SSDT on Supermicro X11SSM-F and verified decompiled version Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46465 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/acpi/acpigen.c | 9 ++++++--- src/soc/intel/skylake/acpi.c | 24 ++++++++++++++++-------- 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 7b7258469f..4a7dfc9325 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -10,6 +10,8 @@ #define ACPIGEN_MAXLEN 0xfffff +#define CPPC_PACKAGE_NAME "GCPC" + #include #include #include @@ -1578,8 +1580,6 @@ void acpigen_write_dsm_uuid_arr(struct dsm_uuid *ids, size_t count) acpigen_pop_len(); /* Method _DSM */ } -#define CPPC_PACKAGE_NAME "\\GCPC" - void acpigen_write_CPPC_package(const struct cppc_config *config) { u32 i; @@ -1621,9 +1621,12 @@ void acpigen_write_CPPC_package(const struct cppc_config *config) void acpigen_write_CPPC_method(void) { + char pscope[16]; + snprintf(pscope, sizeof(pscope), CONFIG_ACPI_CPU_STRING "." CPPC_PACKAGE_NAME, 0); + acpigen_write_method("_CPC", 0); acpigen_emit_byte(RETURN_OP); - acpigen_emit_namestring(CPPC_PACKAGE_NAME); + acpigen_emit_namestring(pscope); acpigen_pop_len(); } diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 637092be97..743b33f9ae 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -369,6 +369,19 @@ static void generate_p_state_entries(int core, int cores_per_package) acpigen_pop_len(); } +static void generate_cppc_entries(int core_id) +{ + /* Generate GCPC table in first logical core */ + if (core_id == 0) { + struct cppc_config cppc_config; + cpu_init_cppc_config(&cppc_config, CPPC_VERSION_2); + acpigen_write_CPPC_package(&cppc_config); + } + + /* Write _CST entry for each logical core */ + acpigen_write_CPPC_method(); +} + void generate_cpu_entries(const struct device *device) { int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; @@ -377,16 +390,11 @@ void generate_cpu_entries(const struct device *device) int numcpus = totalcores/cores_per_package; config_t *config = config_of_soc(); int is_s0ix_enable = config->s0ix_enable; + const bool isst_supported = cpuid_eax(6) & CPUID_6_EAX_ISST; printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); - if (cpuid_eax(6) & CPUID_6_EAX_ISST) { - struct cppc_config cppc_config; - cpu_init_cppc_config(&cppc_config, 2 /* version 2 */); - acpigen_write_CPPC_package(&cppc_config); - } - for (cpu_id = 0; cpu_id < numcpus; cpu_id++) { for (core_id = 0; core_id < cores_per_package; core_id++) { if (core_id > 0) { @@ -407,8 +415,8 @@ void generate_cpu_entries(const struct device *device) cores_per_package); } - if (cpuid_eax(6) & CPUID_6_EAX_ISST) - acpigen_write_CPPC_method(); + if (isst_supported) + generate_cppc_entries(core_id); acpigen_pop_len(); }