soc/intel/xeon_sp/cpx: Add UPI locks

Add UPI locks as indicated by the Intel docs.

Change-Id: I9d1336e57f1776f3024883d6edcf0a855b1382c6
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/intel/xeon_sp/cpx/chip.c

@@ -167,6 +167,13 @@ static void set_imc_locks(void)
 		pci_or_config32(dev, IMC_M2MEM_TIMEOUT, TIMEOUT_LOCK);
 }
 
+static void set_upi_locks(void)
+{
+	struct device *dev = 0;
+	while ((dev = dev_find_device(PCI_VENDOR_ID_INTEL, UPI_LL_CR_DEVID, dev)))
+		pci_or_config32(dev, UPI_LL_CR_KTIMISCMODLCK, KTIMISCMODLCK_LOCK);
+}
+
 static void chip_final(void *data)
 {
 	/* Lock SBI */
@@ -186,6 +193,7 @@ static void chip_final(void *data)
 	mp_run_on_all_cpus(set_msr_locks, NULL);
 	set_pcu_locks();
 	set_imc_locks();
+	set_upi_locks();
 
 	p2sb_hide();
 	iio_enable_masks();

src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h

@@ -124,6 +124,12 @@
 #define IMC_M2MEM_TIMEOUT		0x104
 #define   TIMEOUT_LOCK			BIT(1)
 
+/* UPI Devices */
+/* Bus: B(3), Device: 16,14, Function: 3 (LL_CR) */
+#define UPI_LL_CR_DEVID			0x205B
+#define UPI_LL_CR_KTIMISCMODLCK		0x300
+#define   KTIMISCMODLCK_LOCK		BIT(0)
+
 /* CPU Devices */
 #define CBDMA_DEV_NUM           0x04