broadwell: move to per-device ACPI.
Change-Id: Icc4691f260521e7f3cc9388210c9b7631cf7ce18 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7363 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Vladimir Serbinenko
parent
9acc1e8dfc
commit
b219da8dcf
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@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS
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select TSC_CONSTANT_RATE
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select TSC_SYNC_MFENCE
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select UDELAY_TSC
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select PER_DEVICE_ACPI_TABLES
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config BOOTBLOCK_CPU_INIT
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string
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@ -435,9 +435,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio)
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return (int)power;
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}
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static int generate_P_state_entries(int core, int cores_per_package)
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static void generate_P_state_entries(int core, int cores_per_package)
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{
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int len, len_pss;
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int ratio_min, ratio_max, ratio_turbo, ratio_step;
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int coord_type, power_max, power_unit, num_entries;
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int ratio, power, clock, clock_max;
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@ -472,16 +471,16 @@ static int generate_P_state_entries(int core, int cores_per_package)
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power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
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/* Write _PCT indicating use of FFixedHW */
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len = acpigen_write_empty_PCT();
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acpigen_write_empty_PCT();
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/* Write _PPC with no limit on supported P-state */
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len += acpigen_write_PPC_NVS();
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acpigen_write_PPC_NVS();
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/* Write PSD indicating configured coordination type */
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len += acpigen_write_PSD_package(core, 1, coord_type);
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acpigen_write_PSD_package(core, 1, coord_type);
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/* Add P-state entries in _PSS table */
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len += acpigen_write_name("_PSS");
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acpigen_write_name("_PSS");
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/* Determine ratio points */
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ratio_step = PSS_RATIO_STEP;
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@ -494,13 +493,13 @@ static int generate_P_state_entries(int core, int cores_per_package)
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/* P[T] is Turbo state if enabled */
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if (get_turbo_state() == TURBO_ENABLED) {
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/* _PSS package count including Turbo */
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len_pss = acpigen_write_package(num_entries + 2);
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acpigen_write_package(num_entries + 2);
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msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
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ratio_turbo = msr.lo & 0xff;
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/* Add entry for Turbo ratio */
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len_pss += acpigen_write_PSS_package(
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acpigen_write_PSS_package(
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clock_max + 1, /*MHz*/
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power_max, /*mW*/
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PSS_LATENCY_TRANSITION, /*lat1*/
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@ -509,11 +508,11 @@ static int generate_P_state_entries(int core, int cores_per_package)
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ratio_turbo << 8); /*status*/
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} else {
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/* _PSS package count without Turbo */
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len_pss = acpigen_write_package(num_entries + 1);
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acpigen_write_package(num_entries + 1);
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}
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/* First regular entry is max non-turbo ratio */
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len_pss += acpigen_write_PSS_package(
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acpigen_write_PSS_package(
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clock_max, /*MHz*/
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power_max, /*mW*/
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PSS_LATENCY_TRANSITION, /*lat1*/
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@ -529,7 +528,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
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power = calculate_power(power_max, ratio_max, ratio);
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clock = ratio * CPU_BCLK;
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len_pss += acpigen_write_PSS_package(
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acpigen_write_PSS_package(
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clock, /*MHz*/
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power, /*mW*/
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PSS_LATENCY_TRANSITION, /*lat1*/
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@ -539,15 +538,11 @@ static int generate_P_state_entries(int core, int cores_per_package)
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}
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/* Fix package length */
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len_pss--;
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acpigen_patch_len(len_pss);
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return len + len_pss;
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acpigen_pop_len();
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}
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void generate_cpu_entries(void)
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{
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int len_pr;
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int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6;
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int totalcores = dev_count_cpu();
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int cores_per_package = get_cores_per_package();
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@ -564,23 +559,22 @@ void generate_cpu_entries(void)
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}
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/* Generate processor \_PR.CPUx */
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len_pr = acpigen_write_processor(
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acpigen_write_processor(
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(cpuID-1)*cores_per_package+coreID-1,
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pcontrol_blk, plen);
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/* Generate P-state tables */
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len_pr += generate_P_state_entries(
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generate_P_state_entries(
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coreID-1, cores_per_package);
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/* Generate C-state tables */
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len_pr += generate_C_state_entries();
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generate_C_state_entries();
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/* Generate T-state tables */
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len_pr += generate_T_state_entries(
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generate_T_state_entries(
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cpuID-1, cores_per_package);
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len_pr--;
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acpigen_patch_len(len_pr);
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acpigen_pop_len();
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}
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}
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}
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@ -29,7 +29,8 @@ Name (\PICM, 0) // IOAPIC/8259
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* we have to fix it up in coreboot's ACPI creation phase.
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*/
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OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x2000)
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External(NVSA)
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OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
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Field (GNVS, ByteAcc, NoLock, Preserve)
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{
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/* Miscellaneous */
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@ -62,6 +62,7 @@ typedef struct {
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device_nvs_t dev;
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} __attribute__((packed)) global_nvs_t;
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void acpi_create_gnvs(global_nvs_t *gnvs);
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#ifdef __SMM__
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/* Used in SMM to find the ACPI GNVS address */
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global_nvs_t *smm_get_gnvs(void);
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@ -45,6 +45,9 @@
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#include <broadwell/ramstage.h>
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#include <broadwell/rcba.h>
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#include <chip.h>
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#include <arch/acpi.h>
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#include <arch/acpigen.h>
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#include <cpu/cpu.h>
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static void pch_enable_ioapic(struct device *dev)
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{
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@ -552,10 +555,37 @@ static void pch_lpc_read_resources(device_t dev)
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memset(gnvs, 0, sizeof(global_nvs_t));
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}
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static void southcluster_inject_dsdt(void)
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{
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global_nvs_t *gnvs;
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gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
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if (!gnvs) {
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gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
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if (gnvs)
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memset(gnvs, 0, sizeof(*gnvs));
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}
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if (gnvs) {
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memset(gnvs, 0, sizeof(*gnvs));
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acpi_create_gnvs(gnvs);
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acpi_save_gnvs((unsigned long)gnvs);
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/* And tell SMI about it */
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smm_setup_structures(gnvs, NULL, NULL);
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/* Add it to DSDT. */
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acpigen_write_scope("\\");
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acpigen_write_name_dword("NVSA", (u32) gnvs);
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acpigen_pop_len();
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}
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}
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static struct device_operations device_ops = {
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.read_resources = &pch_lpc_read_resources,
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.set_resources = &pci_dev_set_resources,
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.enable_resources = &pci_dev_enable_resources,
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.acpi_inject_dsdt_generator = southcluster_inject_dsdt,
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.write_acpi_tables = acpi_write_hpet,
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.init = &lpc_init,
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.scan_bus = &scan_static_bus,
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.ops_pci = &broadwell_pci_ops,
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@ -432,8 +432,22 @@ static void systemagent_enable(device_t dev)
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#endif
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}
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unsigned long acpi_fill_slit(unsigned long current)
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{
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// Not implemented
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return current;
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}
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unsigned long acpi_fill_srat(unsigned long current)
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{
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/* No NUMA, no SRAT */
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return current;
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}
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static struct device_operations systemagent_ops = {
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.read_resources = systemagent_read_resources,
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.acpi_fill_ssdt_generator = generate_cpu_entries,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = systemagent_init,
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