broadwell: move to per-device ACPI.

Change-Id: Icc4691f260521e7f3cc9388210c9b7631cf7ce18
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7363
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

src/soc/intel/broadwell/Kconfig

@@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS
 	select TSC_CONSTANT_RATE
 	select TSC_SYNC_MFENCE
 	select UDELAY_TSC
+	select PER_DEVICE_ACPI_TABLES
 
 config BOOTBLOCK_CPU_INIT
 	string

src/soc/intel/broadwell/acpi.c

@@ -435,9 +435,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio)
 	return (int)power;
 }
 
-static int generate_P_state_entries(int core, int cores_per_package)
+static void generate_P_state_entries(int core, int cores_per_package)
 {
-	int len, len_pss;
 	int ratio_min, ratio_max, ratio_turbo, ratio_step;
 	int coord_type, power_max, power_unit, num_entries;
 	int ratio, power, clock, clock_max;
@@ -472,16 +471,16 @@ static int generate_P_state_entries(int core, int cores_per_package)
 	power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
 
 	/* Write _PCT indicating use of FFixedHW */
-	len = acpigen_write_empty_PCT();
+	acpigen_write_empty_PCT();
 
 	/* Write _PPC with no limit on supported P-state */
-	len += acpigen_write_PPC_NVS();
+	acpigen_write_PPC_NVS();
 
 	/* Write PSD indicating configured coordination type */
-	len += acpigen_write_PSD_package(core, 1, coord_type);
+	acpigen_write_PSD_package(core, 1, coord_type);
 
 	/* Add P-state entries in _PSS table */
-	len += acpigen_write_name("_PSS");
+	acpigen_write_name("_PSS");
 
 	/* Determine ratio points */
 	ratio_step = PSS_RATIO_STEP;
@@ -494,13 +493,13 @@ static int generate_P_state_entries(int core, int cores_per_package)
 	/* P[T] is Turbo state if enabled */
 	if (get_turbo_state() == TURBO_ENABLED) {
 		/* _PSS package count including Turbo */
-		len_pss = acpigen_write_package(num_entries + 2);
+		acpigen_write_package(num_entries + 2);
 
 		msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
 		ratio_turbo = msr.lo & 0xff;
 
 		/* Add entry for Turbo ratio */
-		len_pss += acpigen_write_PSS_package(
+		acpigen_write_PSS_package(
 			clock_max + 1,		/*MHz*/
 			power_max,		/*mW*/
 			PSS_LATENCY_TRANSITION,	/*lat1*/
@@ -509,11 +508,11 @@ static int generate_P_state_entries(int core, int cores_per_package)
 			ratio_turbo << 8);	/*status*/
 	} else {
 		/* _PSS package count without Turbo */
-		len_pss = acpigen_write_package(num_entries + 1);
+		acpigen_write_package(num_entries + 1);
 	}
 
 	/* First regular entry is max non-turbo ratio */
-	len_pss += acpigen_write_PSS_package(
+	acpigen_write_PSS_package(
 		clock_max,		/*MHz*/
 		power_max,		/*mW*/
 		PSS_LATENCY_TRANSITION,	/*lat1*/
@@ -529,7 +528,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
 		power = calculate_power(power_max, ratio_max, ratio);
 		clock = ratio * CPU_BCLK;
 
-		len_pss += acpigen_write_PSS_package(
+		acpigen_write_PSS_package(
 			clock,			/*MHz*/
 			power,			/*mW*/
 			PSS_LATENCY_TRANSITION,	/*lat1*/
@@ -539,15 +538,11 @@ static int generate_P_state_entries(int core, int cores_per_package)
 	}
 
 	/* Fix package length */
-	len_pss--;
+	acpigen_pop_len();
-	acpigen_patch_len(len_pss);
-
-	return len + len_pss;
 }
 
 void generate_cpu_entries(void)
 {
-	int len_pr;
 	int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6;
 	int totalcores = dev_count_cpu();
 	int cores_per_package = get_cores_per_package();
@@ -564,23 +559,22 @@ void generate_cpu_entries(void)
 			}
 
 			/* Generate processor \_PR.CPUx */
-			len_pr = acpigen_write_processor(
+			acpigen_write_processor(
 				(cpuID-1)*cores_per_package+coreID-1,
 				pcontrol_blk, plen);
 
 			/* Generate P-state tables */
-			len_pr += generate_P_state_entries(
+			generate_P_state_entries(
 				coreID-1, cores_per_package);
 
 			/* Generate C-state tables */
-			len_pr += generate_C_state_entries();
+			generate_C_state_entries();
 
 			/* Generate T-state tables */
-			len_pr += generate_T_state_entries(
+			generate_T_state_entries(
 				cpuID-1, cores_per_package);
 
-			len_pr--;
+			acpigen_pop_len();
-			acpigen_patch_len(len_pr);
 		}
 	}
 }

src/soc/intel/broadwell/acpi/globalnvs.asl

@@ -29,7 +29,8 @@ Name (\PICM, 0)		// IOAPIC/8259
  * we have to fix it up in coreboot's ACPI creation phase.
  */
 
-OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x2000)
+External(NVSA)
+OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */

src/soc/intel/broadwell/broadwell/nvs.h

@@ -62,6 +62,7 @@ typedef struct {
 	device_nvs_t dev;
 } __attribute__((packed)) global_nvs_t;
 
+void acpi_create_gnvs(global_nvs_t *gnvs);
 #ifdef __SMM__
 /* Used in SMM to find the ACPI GNVS address */
 global_nvs_t *smm_get_gnvs(void);

src/soc/intel/broadwell/lpc.c

@@ -45,6 +45,9 @@
 #include <broadwell/ramstage.h>
 #include <broadwell/rcba.h>
 #include <chip.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <cpu/cpu.h>
 
 static void pch_enable_ioapic(struct device *dev)
 {
@@ -552,10 +555,37 @@ static void pch_lpc_read_resources(device_t dev)
 		memset(gnvs, 0, sizeof(global_nvs_t));
 }
 
+static void southcluster_inject_dsdt(void)
+{
+	global_nvs_t *gnvs;
+
+	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
+	if (!gnvs) {
+		gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
+		if (gnvs)
+			memset(gnvs, 0, sizeof(*gnvs));
+	}
+
+	if (gnvs) {
+		memset(gnvs, 0, sizeof(*gnvs));
+		acpi_create_gnvs(gnvs);
+		acpi_save_gnvs((unsigned long)gnvs);
+		/* And tell SMI about it */
+		smm_setup_structures(gnvs, NULL, NULL);
+
+		/* Add it to DSDT.  */
+		acpigen_write_scope("\\");
+		acpigen_write_name_dword("NVSA", (u32) gnvs);
+		acpigen_pop_len();
+	}
+}
+
 static struct device_operations device_ops = {
 	.read_resources		= &pch_lpc_read_resources,
 	.set_resources		= &pci_dev_set_resources,
 	.enable_resources	= &pci_dev_enable_resources,
+	.acpi_inject_dsdt_generator = southcluster_inject_dsdt,
+	.write_acpi_tables      = acpi_write_hpet,
 	.init			= &lpc_init,
 	.scan_bus		= &scan_static_bus,
 	.ops_pci		= &broadwell_pci_ops,

src/soc/intel/broadwell/systemagent.c

@@ -432,8 +432,22 @@ static void systemagent_enable(device_t dev)
 #endif
 }
 
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+	return current;
+}
+
 static struct device_operations systemagent_ops = {
 	.read_resources   = systemagent_read_resources,
+	.acpi_fill_ssdt_generator = generate_cpu_entries,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = systemagent_init,