sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASE

Make it default to 0x400, which is what the touched southbridges use.

Change-Id: I95cb1730d5bf6f596ed1ca8e7dba40b6a9e882fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/mainboard/asus/p8z77-m_pro/early_init.c

@@ -89,7 +89,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 		.dmibar = (uintptr_t)DEFAULT_DMIBAR,
 		.epbar = DEFAULT_EPBAR,
 		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
-		.smbusbar = SMBUS_IO_BASE,
+		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
 		.wdbbar = 0x4000000,
 		.wdbsize = 0x1000,
 		.hpet_address = CONFIG_HPET_ADDRESS,

src/mainboard/google/butterfly/early_init.c

@@ -83,7 +83,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 		.dmibar = (uintptr_t)DEFAULT_DMIBAR,
 		.epbar = DEFAULT_EPBAR,
 		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
-		.smbusbar = SMBUS_IO_BASE,
+		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
 		.wdbbar = 0x4000000,
 		.wdbsize = 0x1000,
 		.hpet_address = CONFIG_HPET_ADDRESS,

src/mainboard/google/link/early_init.c

@@ -90,7 +90,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 		.dmibar = (uintptr_t)DEFAULT_DMIBAR,
 		.epbar = DEFAULT_EPBAR,
 		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
-		.smbusbar = SMBUS_IO_BASE,
+		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
 		.wdbbar = 0x4000000,
 		.wdbsize = 0x1000,
 		.hpet_address = CONFIG_HPET_ADDRESS,

src/mainboard/google/parrot/early_init.c

@@ -58,7 +58,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 		.dmibar = (uintptr_t)DEFAULT_DMIBAR,
 		.epbar = DEFAULT_EPBAR,
 		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
-		.smbusbar = SMBUS_IO_BASE,
+		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
 		.wdbbar = 0x4000000,
 		.wdbsize = 0x1000,
 		.hpet_address = CONFIG_HPET_ADDRESS,

src/mainboard/google/stout/early_init.c

@@ -95,7 +95,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 		.dmibar = (uintptr_t)DEFAULT_DMIBAR,
 		.epbar = DEFAULT_EPBAR,
 		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
-		.smbusbar = SMBUS_IO_BASE,
+		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
 		.wdbbar = 0x4000000,
 		.wdbsize = 0x1000,
 		.hpet_address = CONFIG_HPET_ADDRESS,

src/mainboard/intel/dcp847ske/romstage.c

@@ -18,7 +18,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 		.dmibar = (uintptr_t)DEFAULT_DMIBAR,
 		.epbar = DEFAULT_EPBAR,
 		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
-		.smbusbar = SMBUS_IO_BASE,
+		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
 		.wdbbar = 0x4000000,
 		.wdbsize = 0x1000,
 		.hpet_address = CONFIG_HPET_ADDRESS,

src/mainboard/intel/emeraldlake2/early_init.c

@@ -55,7 +55,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 		.dmibar = (uintptr_t)DEFAULT_DMIBAR,
 		.epbar = DEFAULT_EPBAR,
 		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
-		.smbusbar = SMBUS_IO_BASE,
+		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
 		.wdbbar = 0x4000000,
 		.wdbsize = 0x1000,
 		.hpet_address = CONFIG_HPET_ADDRESS,

src/mainboard/kontron/ktqm77/early_init.c

@@ -58,7 +58,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 		.dmibar = (uintptr_t)DEFAULT_DMIBAR,
 		.epbar = DEFAULT_EPBAR,
 		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
-		.smbusbar = SMBUS_IO_BASE,
+		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
 		.wdbbar = 0x4000000,
 		.wdbsize = 0x1000,
 		.hpet_address = CONFIG_HPET_ADDRESS,

src/mainboard/lenovo/x220/early_init.c

@@ -16,7 +16,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 		.dmibar = (uintptr_t)DEFAULT_DMIBAR,
 		.epbar = DEFAULT_EPBAR,
 		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
-		.smbusbar = SMBUS_IO_BASE,
+		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
 		.wdbbar = 0x4000000,
 		.wdbsize = 0x1000,
 		.hpet_address = CONFIG_HPET_ADDRESS,

src/mainboard/roda/rv11/variants/rv11/early_init.c

@@ -14,7 +14,7 @@ void mainboard_fill_pei_data(struct pei_data *const pei_data)
 		.dmibar = (uintptr_t)DEFAULT_DMIBAR,
 		.epbar = DEFAULT_EPBAR,
 		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
-		.smbusbar = SMBUS_IO_BASE,
+		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
 		.wdbbar = 0x4000000,
 		.wdbsize = 0x1000,
 		.hpet_address = CONFIG_HPET_ADDRESS,

src/mainboard/roda/rv11/variants/rw11/early_init.c

@@ -44,7 +44,7 @@ void mainboard_fill_pei_data(struct pei_data *const pei_data)
 		.dmibar = (uintptr_t)DEFAULT_DMIBAR,
 		.epbar = DEFAULT_EPBAR,
 		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
-		.smbusbar = SMBUS_IO_BASE,
+		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
 		.wdbbar = 0x4000000,
 		.wdbsize = 0x1000,
 		.hpet_address = CONFIG_HPET_ADDRESS,

src/mainboard/samsung/lumpy/early_init.c

@@ -121,7 +121,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 		.dmibar = (uintptr_t)DEFAULT_DMIBAR,
 		.epbar = DEFAULT_EPBAR,
 		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
-		.smbusbar = SMBUS_IO_BASE,
+		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
 		.wdbbar = 0x4000000,
 		.wdbsize = 0x1000,
 		.hpet_address = CONFIG_HPET_ADDRESS,

src/mainboard/samsung/stumpy/early_init.c

@@ -105,7 +105,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 		.dmibar = (uintptr_t)DEFAULT_DMIBAR,
 		.epbar = DEFAULT_EPBAR,
 		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
-		.smbusbar = SMBUS_IO_BASE,
+		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
 		.wdbbar = 0x4000000,
 		.wdbsize = 0x1000,
 		.hpet_address = CONFIG_HPET_ADDRESS,

src/northbridge/intel/haswell/romstage.c

@@ -51,7 +51,7 @@ void mainboard_romstage_entry(void)
 		.dmibar			= (uintptr_t)DEFAULT_DMIBAR,
 		.epbar			= DEFAULT_EPBAR,
 		.pciexbar		= CONFIG_MMCONF_BASE_ADDRESS,
-		.smbusbar		= SMBUS_IO_BASE,
+		.smbusbar		= CONFIG_FIXED_SMBUS_IO_BASE,
 		.hpet_address		= HPET_ADDR,
 		.rcba			= (uintptr_t)DEFAULT_RCBA,
 		.pmbase			= DEFAULT_PMBASE,

src/northbridge/intel/sandybridge/raminit_mrc.c

@@ -251,7 +251,7 @@ static void southbridge_fill_pei_data(struct pei_data *pei_data)
 {
 	const struct device *dev = pcidev_on_root(0x19, 0);
 
-	pei_data->smbusbar   = SMBUS_IO_BASE;
+	pei_data->smbusbar   = CONFIG_FIXED_SMBUS_IO_BASE;
 	pei_data->wdbbar     = 0x04000000;
 	pei_data->wdbsize    = 0x1000;
 	pei_data->rcba       = (uintptr_t)DEFAULT_RCBABASE;

src/southbridge/intel/bd82x6x/early_smbus.c

@@ -8,7 +8,7 @@
 
 uintptr_t smbus_base(void)
 {
-	return SMBUS_IO_BASE;
+	return CONFIG_FIXED_SMBUS_IO_BASE;
 }
 
 int smbus_enable_iobar(uintptr_t base)

src/southbridge/intel/bd82x6x/pch.h

@@ -21,11 +21,10 @@
  * It does not matter where we put the SMBus I/O base, as long as we
  * keep it consistent and don't interfere with other devices.  Stage2
  * will relocate this anyways.
- * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
+ * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE
  * again. But handling static BARs is a generic problem that should be
  * solved in the device allocator.
  */
-#define SMBUS_IO_BASE		0x0400
 #define SMBUS_SLAVE_ADDR	0x24
 /* TODO Make sure these don't get changed by stage2 */
 #define DEFAULT_GPIOBASE	0x0480

src/southbridge/intel/bd82x6x/smbus.c

@@ -60,7 +60,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
 static void smbus_read_resources(struct device *dev)
 {
 	struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
-	res->base = SMBUS_IO_BASE;
+	res->base = CONFIG_FIXED_SMBUS_IO_BASE;
 	res->size = 32;
 	res->limit = res->base + res->size - 1;
 	res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |

src/southbridge/intel/common/Kconfig

@@ -97,3 +97,8 @@ config INTEL_CHIPSET_LOCKDOWN
 config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
 	bool
 	depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE
+
+config FIXED_SMBUS_IO_BASE
+	hex
+	depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS
+	default 0x400

src/southbridge/intel/i82801dx/early_smbus.c

@@ -12,7 +12,7 @@ void i82801dx_early_init(void)
 
 uintptr_t smbus_base(void)
 {
-	return SMBUS_IO_BASE;
+	return CONFIG_FIXED_SMBUS_IO_BASE;
 }
 
 int smbus_enable_iobar(uintptr_t base)

src/southbridge/intel/i82801dx/i82801dx.h

@@ -94,8 +94,6 @@ void aseg_smm_lock(void);
 #define RTC_FAILED      (1 <<2)
 
 
-#define SMBUS_IO_BASE	0x400
-
 #define PM1_STS		0x00
 #define   WAK_STS	(1 << 15)
 #define   PCIEXPWAK_STS	(1 << 14)

src/southbridge/intel/i82801gx/early_smbus.c

@@ -7,7 +7,7 @@
 
 uintptr_t smbus_base(void)
 {
-	return SMBUS_IO_BASE;
+	return CONFIG_FIXED_SMBUS_IO_BASE;
 }
 
 int smbus_enable_iobar(uintptr_t base)

src/southbridge/intel/i82801gx/i82801gx.h

@@ -7,11 +7,10 @@
  * It does not matter where we put the SMBus I/O base, as long as we
  * keep it consistent and don't interfere with other devices.  Stage2
  * will relocate this anyways.
- * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
+ * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE
  * again. But handling static BARs is a generic problem that should be
  * solved in the device allocator.
  */
-#define SMBUS_IO_BASE		0x0400
 /* TODO Make sure these don't get changed by stage2 */
 #define DEFAULT_GPIOBASE	0x0480
 #define DEFAULT_PMBASE		0x0500

src/southbridge/intel/i82801gx/smbus.c

@@ -68,7 +68,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
 static void smbus_read_resources(struct device *dev)
 {
 	struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
-	res->base = SMBUS_IO_BASE;
+	res->base = CONFIG_FIXED_SMBUS_IO_BASE;
 	res->size = 32;
 	res->limit = res->base + res->size - 1;
 	res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |

src/southbridge/intel/i82801ix/early_smbus.c

@@ -8,7 +8,7 @@
 
 uintptr_t smbus_base(void)
 {
-	return SMBUS_IO_BASE;
+	return CONFIG_FIXED_SMBUS_IO_BASE;
 }
 
 int smbus_enable_iobar(uintptr_t base)

src/southbridge/intel/i82801ix/i82801ix.h

@@ -80,8 +80,6 @@
 #define D28Fx_SLCAP		0x54
 
 
-#define SMBUS_IO_BASE		0x0400
-
 /* PCI Configuration Space (D31:F3): SMBus */
 #define SMB_BASE		0x20
 #define HOSTC			0x40

src/southbridge/intel/i82801ix/lpc.c

@@ -424,7 +424,7 @@ static void i82801ix_lpc_read_resources(struct device *dev)
 	 * 0x00c0 ~ 0x00de....ISA DMA
 	 * 0x00c1 ~ 0x00df....ISA DMA aliases
 	 * 0x00f0.............Coprocessor Error
-	 * (0x0400-0x041f)....SMBus (SMBUS_IO_BASE, during raminit)
+	 * (0x0400-0x041f)....SMBus (CONFIG_FIXED_SMBUS_IO_BASE, during raminit)
 	 * 0x04d0 - 0x04d1....PIC
 	 * 0x0500 - 0x057f....PM (DEFAULT_PMBASE)
 	 * 0x0580 - 0x05bf....SB GPIO (DEFAULT_GPIOBASE)

src/southbridge/intel/i82801ix/smbus.c

@@ -49,7 +49,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
 static void smbus_read_resources(struct device *dev)
 {
 	struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
-	res->base = SMBUS_IO_BASE;
+	res->base = CONFIG_FIXED_SMBUS_IO_BASE;
 	res->size = 32;
 	res->limit = res->base + res->size - 1;
 	res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |

src/southbridge/intel/i82801jx/early_smbus.c

@@ -7,7 +7,7 @@
 
 uintptr_t smbus_base(void)
 {
-	return SMBUS_IO_BASE;
+	return CONFIG_FIXED_SMBUS_IO_BASE;
 }
 
 int smbus_enable_iobar(uintptr_t base)

src/southbridge/intel/i82801jx/i82801jx.h

@@ -83,8 +83,6 @@
 #define D28Fx_SLCAP		0x54
 
 
-#define SMBUS_IO_BASE		0x0400
-
 /* PCI Configuration Space (D31:F3): SMBus */
 #define SMB_BASE		0x20
 #define HOSTC			0x40

src/southbridge/intel/i82801jx/lpc.c

@@ -451,7 +451,7 @@ static void i82801jx_lpc_read_resources(struct device *dev)
 	 * 0x00c0 ~ 0x00de....ISA DMA
 	 * 0x00c1 ~ 0x00df....ISA DMA aliases
 	 * 0x00f0.............Coprocessor Error
-	 * (0x0400-0x041f)....SMBus (SMBUS_IO_BASE, during raminit)
+	 * (0x0400-0x041f)....SMBus (CONFIG_FIXED_SMBUS_IO_BASE, during raminit)
 	 * 0x04d0 - 0x04d1....PIC
 	 * 0x0500 - 0x057f....PM (DEFAULT_PMBASE)
 	 * 0x0580 - 0x05bf....SB GPIO (DEFAULT_GPIOBASE)

src/southbridge/intel/i82801jx/smbus.c

@@ -76,7 +76,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
 static void smbus_read_resources(struct device *dev)
 {
 	struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
-	res->base = SMBUS_IO_BASE;
+	res->base = CONFIG_FIXED_SMBUS_IO_BASE;
 	res->size = 32;
 	res->limit = res->base + res->size - 1;
 	res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |

src/southbridge/intel/ibexpeak/early_smbus.c

@@ -8,7 +8,7 @@
 
 uintptr_t smbus_base(void)
 {
-	return SMBUS_IO_BASE;
+	return CONFIG_FIXED_SMBUS_IO_BASE;
 }
 
 int smbus_enable_iobar(uintptr_t base)

src/southbridge/intel/ibexpeak/pch.h

@@ -22,11 +22,10 @@
  * It does not matter where we put the SMBus I/O base, as long as we
  * keep it consistent and don't interfere with other devices.  Stage2
  * will relocate this anyways.
- * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
+ * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE
  * again. But handling static BARs is a generic problem that should be
  * solved in the device allocator.
  */
-#define SMBUS_IO_BASE		0x0400
 #define SMBUS_SLAVE_ADDR	0x24
 /* TODO Make sure these don't get changed by stage2 */
 #define DEFAULT_GPIOBASE	0x0480

src/southbridge/intel/ibexpeak/smbus.c

@@ -59,7 +59,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
 static void smbus_read_resources(struct device *dev)
 {
 	struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
-	res->base = SMBUS_IO_BASE;
+	res->base = CONFIG_FIXED_SMBUS_IO_BASE;
 	res->size = 32;
 	res->limit = res->base + res->size - 1;
 	res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |

src/southbridge/intel/lynxpoint/early_smbus.c

@@ -8,7 +8,7 @@
 
 uintptr_t smbus_base(void)
 {
-	return SMBUS_IO_BASE;
+	return CONFIG_FIXED_SMBUS_IO_BASE;
 }
 
 int smbus_enable_iobar(uintptr_t base)

src/southbridge/intel/lynxpoint/pch.h

@@ -47,11 +47,10 @@
  * It does not matter where we put the SMBus I/O base, as long as we
  * keep it consistent and don't interfere with other devices.  Stage2
  * will relocate this anyways.
- * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
+ * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE
  * again. But handling static BARs is a generic problem that should be
  * solved in the device allocator.
  */
-#define SMBUS_IO_BASE		0x0400
 #define SMBUS_SLAVE_ADDR	0x24
 
 #if CONFIG(INTEL_LYNXPOINT_LP)

src/southbridge/intel/lynxpoint/smbus.c

@@ -58,7 +58,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
 static void smbus_read_resources(struct device *dev)
 {
 	struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
-	res->base = SMBUS_IO_BASE;
+	res->base = CONFIG_FIXED_SMBUS_IO_BASE;
 	res->size = 32;
 	res->limit = res->base + res->size - 1;
 	res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |