mainboard/winnet/g170: Add ACPI support

What is present is APIC and legacy interrupt routing and the soft-off sleep
state. Other sleep states are missing, so are the SuperIO devices.

Boots Linux with and without "noapic" and a Windows XP (installed with
factory BIOS, the installer reportedly requires legacy keyboard).

Change-Id: Iee3ede8683d1ea51317228d4f782af27043cc945
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Lubomir Rintel 2017-03-18 19:29:28 +01:00 committed by Martin Roth
parent 24512dee2b
commit b233916f50
3 changed files with 95 additions and 0 deletions

View File

@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS
select SUPERIO_WINBOND_W83697HF
select HAVE_PIRQ_TABLE
select HAVE_OPTION_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_512
config MAINBOARD_DIR

View File

@ -0,0 +1,51 @@
/*
* This file is part of the coreboot project.
*
* Based on mainboard/via/epia-m700/acpi_tables.c
*
* Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
* Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
* Copyright (C) 2017 Lubomir Rintel <lkundrak@v3.sk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <arch/acpi.h>
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include "southbridge/via/vt8237r/vt8237r.h"
unsigned long acpi_fill_mcfg(unsigned long current)
{
return current;
}
unsigned long acpi_fill_madt(unsigned long current)
{
/* Create all subtables for processors. */
current = acpi_create_madt_lapics(current);
/* Write SB IOAPIC. */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
VT8237R_APIC_ID, IO_APIC_ADDR, 0);
/* IRQ9 ACPI active low. */
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
/* IRQ0 -> APIC IRQ2. */
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0x0);
return current;
}

View File

@ -0,0 +1,43 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Lubomir Rintel <lkundrak@v3.sk>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20170227 // OEM revision
)
{
/* Sleep states */
Name (\_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 })
Name (\_S5, Package (0x04) { 0x02, 0x02, 0x02, 0x02 })
/* Interrupt model */
Method (_PIC, 1) {
Store (Arg0, \_SB.PCI0.ISAC.APIC)
}
Scope (\_SB) {
/* PCI bus */
Device (PCI0) {
#include <northbridge/via/cn700/acpi/hostbridge.asl>
#include <southbridge/via/vt8237r/acpi/lpc.asl>
#include <southbridge/via/vt8237r/acpi/default_irq_route.asl>
}
}
}