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sb/intel/i82801gx: Add a function to set up BAR 

This removes some of the sb code in the nb.

Change-Id: I2ab894be93f210220fa55ddd10cd48889f308e5b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This commit is contained in:
Arthur Heymans 2019-11-11 18:40:50 +01:00 committed by Patrick Georgi
parent 0d92271d2c
commit b236352281
5 changed files with 17 additions and 13 deletions
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5
src/northbridge/intel/i945/early_init.c
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@ -159,11 +159,8 @@ static void i945_setup_bars(void)
/* Setting up Southbridge. In the northbridge code. */
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, ACPI_EN);
i82801gx_setup_bars();
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
pci_write_config8(PCI_DEV(0, 0x1f, 0), GPIO_CNTL, GPIO_EN);
setup_pch_gpios(&mainboard_gpio_map);
printk(BIOS_DEBUG, " done.\n");

8
src/northbridge/intel/pineview/early_init.c
View File

@ -158,12 +158,8 @@ static void pineview_setup_bars(void)
{
/* Setting up Southbridge. In the northbridge code. */
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
pci_write_config32(LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(LPC, PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(LPC, 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI */
pci_write_config32(LPC, GPIOBASE, DEFAULT_GPIOBASE | 1);
pci_write_config8(LPC, 0x4c /* GC */, 0x10); /* Enable GPIOs */
pci_write_config32(LPC, 0x88, 0x007c0291);
i82801gx_setup_bars();
pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
printk(BIOS_DEBUG, " done.\n");

4
src/southbridge/intel/i82801gx/bootblock_gcc.c
View File

@ -32,9 +32,7 @@ void bootblock_early_southbridge_init(void)
{
enable_spi_prefetch();
/* Enable RCBA */
pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0);
pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
i82801gx_setup_bars();
/* Enable upper 128bytes of CMOS */
RCBA32(0x3400) = (1 << 2);

12
src/southbridge/intel/i82801gx/early_init.c
View File

@ -11,6 +11,7 @@
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <device/pci_ops.h>
#include "i82801gx.h"
#include "chip.h"
@ -50,3 +51,14 @@ void i82801gx_lpc_setup(void)
pci_write_config32(d31f0, GEN3_DEC, config->gen3_dec);
pci_write_config32(d31f0, GEN4_DEC, config->gen4_dec);
}
void i82801gx_setup_bars(void)
{
const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
pci_write_config32(d31f0, RCBA, (uint32_t)DEFAULT_RCBA | 1);
pci_write_config32(d31f0, PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(d31f0, ACPI_CNTL, ACPI_EN);
pci_write_config32(d31f0, GPIOBASE, DEFAULT_GPIOBASE | 1);
pci_write_config8(d31f0, GPIO_CNTL, GPIO_EN);
}

1
src/southbridge/intel/i82801gx/i82801gx.h
View File

@ -41,6 +41,7 @@ void i82801gx_enable(struct device *dev);
void enable_smbus(void);
void i82801gx_lpc_setup(void);
void i82801gx_setup_bars(void);
#if ENV_ROMSTAGE
int smbus_read_byte(unsigned int device, unsigned int address);