sb/intel/i82801gx: Add a function to set up BAR
This removes some of the sb code in the nb. Change-Id: I2ab894be93f210220fa55ddd10cd48889f308e5b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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@ -159,11 +159,8 @@ static void i945_setup_bars(void)
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/* Setting up Southbridge. In the northbridge code. */
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printk(BIOS_DEBUG, "Setting up static southbridge registers...");
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pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, ACPI_EN);
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i82801gx_setup_bars();
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pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), GPIO_CNTL, GPIO_EN);
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setup_pch_gpios(&mainboard_gpio_map);
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printk(BIOS_DEBUG, " done.\n");
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@ -158,12 +158,8 @@ static void pineview_setup_bars(void)
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{
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/* Setting up Southbridge. In the northbridge code. */
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printk(BIOS_DEBUG, "Setting up static southbridge registers...");
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pci_write_config32(LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
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pci_write_config32(LPC, PMBASE, DEFAULT_PMBASE | 1);
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pci_write_config8(LPC, 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI */
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pci_write_config32(LPC, GPIOBASE, DEFAULT_GPIOBASE | 1);
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pci_write_config8(LPC, 0x4c /* GC */, 0x10); /* Enable GPIOs */
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pci_write_config32(LPC, 0x88, 0x007c0291);
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i82801gx_setup_bars();
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pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
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printk(BIOS_DEBUG, " done.\n");
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@ -32,9 +32,7 @@ void bootblock_early_southbridge_init(void)
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{
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enable_spi_prefetch();
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/* Enable RCBA */
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pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0);
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pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
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i82801gx_setup_bars();
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/* Enable upper 128bytes of CMOS */
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RCBA32(0x3400) = (1 << 2);
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@ -11,6 +11,7 @@
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <device/pci_ops.h>
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#include "i82801gx.h"
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#include "chip.h"
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@ -50,3 +51,14 @@ void i82801gx_lpc_setup(void)
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pci_write_config32(d31f0, GEN3_DEC, config->gen3_dec);
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pci_write_config32(d31f0, GEN4_DEC, config->gen4_dec);
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}
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void i82801gx_setup_bars(void)
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{
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const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
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pci_write_config32(d31f0, RCBA, (uint32_t)DEFAULT_RCBA | 1);
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pci_write_config32(d31f0, PMBASE, DEFAULT_PMBASE | 1);
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pci_write_config8(d31f0, ACPI_CNTL, ACPI_EN);
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pci_write_config32(d31f0, GPIOBASE, DEFAULT_GPIOBASE | 1);
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pci_write_config8(d31f0, GPIO_CNTL, GPIO_EN);
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}
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@ -41,6 +41,7 @@ void i82801gx_enable(struct device *dev);
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void enable_smbus(void);
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void i82801gx_lpc_setup(void);
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void i82801gx_setup_bars(void);
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#if ENV_ROMSTAGE
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int smbus_read_byte(unsigned int device, unsigned int address);
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