mb/*/{brya,adlrvp}: move cpu_cluster static configuration to chipset.cb

For mainboard devicetree, it always have definition for enabling
cpu_cluster 0 which is required for all the variants.
Since it is SoC related settings, it's better to keep in chipset.cb
as a common setting for all the mainboards using the same SoC.

BUG=None
BRANCH=None
TEST=Change has no functional impact on the brya board.

Change-Id: I8f7c3184b62f8d84ca4605fb9f2a1cc569f1f964
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56853
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb

@@ -1,7 +1,5 @@
 chip soc/intel/alderlake
 
-	device cpu_cluster 0 on end
-
 	# GPE configuration
 	register "pmc_gpe0_dw0" = "GPP_A"
 	register "pmc_gpe0_dw1" = "GPP_E"

src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb

@@ -1,7 +1,5 @@
 chip soc/intel/alderlake
 
-	device cpu_cluster 0 on end
-
 	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
 
 	# GPE configuration

src/mainboard/intel/adlrvp/devicetree.cb

@@ -1,7 +1,5 @@
 chip soc/intel/alderlake
 
-	device cpu_cluster 0 on end
-
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this
 	# route. i.e. If this route changes then the affected GPE

src/mainboard/intel/adlrvp/devicetree_m.cb

@@ -6,8 +6,6 @@ fw_config
 end
 chip soc/intel/alderlake
 
-	device cpu_cluster 0 on end
-
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this
 	# route. i.e. If this route changes then the affected GPE

src/soc/intel/alderlake/chipset.cb

@@ -1,5 +1,7 @@
 chip soc/intel/alderlake
 
+	device cpu_cluster 0 on end
+
 	register "power_limits_config[ADL_P_POWER_LIMITS_282_CORE]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 55,