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Change read_option() to a macro that wraps some API uglyness 

Simplify
read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault)
to
read_option(foo, somedefault)

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2011-05-10 21:53:13 +00:00 committed by Patrick Georgi
parent 6649d9740d
commit b251753b4f
15 changed files with 24 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/amd/dualcore/dualcore.c
View File

@ -49,7 +49,7 @@ static inline void start_other_cores(void)
unsigned nodes; unsigned nodes;
unsigned nodeid; unsigned nodeid;
if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0)) { if (read_option(multi_core, 0)) {
return; // disable multi_core return; // disable multi_core
} }

2
src/cpu/amd/model_10xxx/init_cpus.c
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@ -72,7 +72,7 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
nodes = get_nodes(); nodes = get_nodes();
if (!CONFIG_LOGICAL_CPUS || if (!CONFIG_LOGICAL_CPUS ||
read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 means multi core read_option(multi_core, 0) != 0) { // 0 means multi core
disable_siblings = 1; disable_siblings = 1;
} else { } else {
disable_siblings = 0; disable_siblings = 0;

2
src/cpu/amd/model_fxx/init_cpus.c
View File

@ -25,7 +25,7 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
nodes = get_nodes(); nodes = get_nodes();
if (!CONFIG_LOGICAL_CPUS || if (!CONFIG_LOGICAL_CPUS ||
read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 means multi core read_option(multi_core, 0) != 0) { // 0 means multi core
disable_siblings = 1; disable_siblings = 1;
} else { } else {
disable_siblings = 0; disable_siblings = 0;

2
src/cpu/amd/quadcore/quadcore.c
View File

@ -82,7 +82,7 @@ static void start_other_cores(void)
u32 nodeid; u32 nodeid;
// disable multi_core // disable multi_core
if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { if (read_option(multi_core, 0) != 0) {
printk(BIOS_DEBUG, "Skip additional core init\n"); printk(BIOS_DEBUG, "Skip additional core init\n");
return; return;
} }

5
src/include/pc80/mc146818rtc.h
View File

@ -110,15 +110,16 @@ static inline void cmos_write(unsigned char val, unsigned char addr)
void rtc_init(int invalid); void rtc_init(int invalid);
#if CONFIG_USE_OPTION_TABLE #if CONFIG_USE_OPTION_TABLE
int get_option(void *dest, const char *name); int get_option(void *dest, const char *name);
unsigned read_option(unsigned start, unsigned size, unsigned def); unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def);
#else #else
static inline int get_option(void *dest __attribute__((unused)), static inline int get_option(void *dest __attribute__((unused)),
const char *name __attribute__((unused))) { return -2; } const char *name __attribute__((unused))) { return -2; }
static inline unsigned read_option(unsigned start, unsigned size, unsigned def) static inline unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def)
{ return def; } { return def; }
#endif #endif
#else #else
#include <pc80/mc146818rtc_early.c> #include <pc80/mc146818rtc_early.c>
#endif #endif
#define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, CMOS_VLEN_ ##name, (default))
#endif /* PC80_MC146818RTC_H */ #endif /* PC80_MC146818RTC_H */

2
src/lib/uart8250.c
View File

@ -99,7 +99,7 @@ void uart_init(void)
static const unsigned char divisor[8] = { 1, 2, 3, 6, 12, 24, 48, 96 }; static const unsigned char divisor[8] = { 1, 2, 3, 6, 12, 24, 48, 96 };
unsigned b_index = 0; unsigned b_index = 0;
#if defined(__PRE_RAM__) #if defined(__PRE_RAM__)
b_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0); b_index = read_option(baud_rate, 0);
b_index &= 7; b_index &= 7;
div = divisor[b_index]; div = divisor[b_index];
#else #else

2
src/mainboard/getac/p470/romstage.c
View File

@ -83,7 +83,7 @@ void setup_ich7_gpios(void)
static void ich7_enable_lpc(void) static void ich7_enable_lpc(void)
{ {
int lpt_en = 0; int lpt_en = 0;
if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) { if (read_option(lpt, 0) != 0) {
lpt_en = 1<<2; // enable LPT lpt_en = 1<<2; // enable LPT
} }
// Enable Serial IRQ // Enable Serial IRQ

8
src/mainboard/kontron/986lcd-m/romstage.c
View File

@ -59,7 +59,7 @@ void setup_ich7_gpios(void)
static void ich7_enable_lpc(void) static void ich7_enable_lpc(void)
{ {
int lpt_en = 0; int lpt_en = 0;
if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) { if (read_option(lpt, 0) != 0) {
lpt_en = 1<<2; // enable LPT lpt_en = 1<<2; // enable LPT
} }
// Enable Serial IRQ // Enable Serial IRQ
@ -228,18 +228,18 @@ static void rcba_config(void)
reg32 = FD_ACMOD|FD_ACAUD|FD_PATA; reg32 = FD_ACMOD|FD_ACAUD|FD_PATA;
reg32 |= FD_PCIE6|FD_PCIE5|FD_PCIE4; reg32 |= FD_PCIE6|FD_PCIE5|FD_PCIE4;
if (read_option(CMOS_VSTART_ethernet1, CMOS_VLEN_ethernet1, 0) != 0) { if (read_option(ethernet1, 0) != 0) {
printk(BIOS_DEBUG, "Disabling ethernet adapter 1.\n"); printk(BIOS_DEBUG, "Disabling ethernet adapter 1.\n");
reg32 |= FD_PCIE1; reg32 |= FD_PCIE1;
} }
if (read_option(CMOS_VSTART_ethernet2, CMOS_VLEN_ethernet2, 0) != 0) { if (read_option(ethernet2, 0) != 0) {
printk(BIOS_DEBUG, "Disabling ethernet adapter 2.\n"); printk(BIOS_DEBUG, "Disabling ethernet adapter 2.\n");
reg32 |= FD_PCIE2; reg32 |= FD_PCIE2;
} else { } else {
if (reg32 & FD_PCIE1) if (reg32 & FD_PCIE1)
port_shuffle = 1; port_shuffle = 1;
} }
if (read_option(CMOS_VSTART_ethernet3, CMOS_VLEN_ethernet3, 0) != 0) { if (read_option(ethernet3, 0) != 0) {
printk(BIOS_DEBUG, "Disabling ethernet adapter 3.\n"); printk(BIOS_DEBUG, "Disabling ethernet adapter 3.\n");
reg32 |= FD_PCIE3; reg32 |= FD_PCIE3;
} else { } else {

2
src/mainboard/roda/rk886ex/romstage.c
View File

@ -70,7 +70,7 @@ void setup_ich7_gpios(void)
static void ich7_enable_lpc(void) static void ich7_enable_lpc(void)
{ {
int lpt_en = 0; int lpt_en = 0;
if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) { if (read_option(lpt, 0) != 0) {
lpt_en = 1<<2; // enable LPT lpt_en = 1<<2; // enable LPT
} }
// Enable Serial IRQ // Enable Serial IRQ

2
src/northbridge/amd/amdk8/coherent_ht.c
View File

@ -1599,7 +1599,7 @@ static void coherent_ht_finalize(unsigned nodes)
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
unsigned total_cpus; unsigned total_cpus;
if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) == 0) { /* multi_core */ if (read_option(multi_core, 0) == 0) { /* multi_core */
total_cpus = verify_dualcore(nodes); total_cpus = verify_dualcore(nodes);
} }
else { else {

6
src/northbridge/amd/amdk8/raminit.c
View File

@ -548,7 +548,7 @@ static void hw_enable_ecc(const struct mem_controller *ctrl)
if (nbcap & NBCAP_ECC) { if (nbcap & NBCAP_ECC) {
dcl |= DCL_DimmEccEn; dcl |= DCL_DimmEccEn;
} }
if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { if (read_option(ECC_memory, 1) == 0) {
dcl &= ~DCL_DimmEccEn; dcl &= ~DCL_DimmEccEn;
} }
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
@ -1100,7 +1100,7 @@ static void order_dimms(const struct mem_controller *ctrl)
{ {
unsigned long tom_k, base_k; unsigned long tom_k, base_k;
if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) { if (read_option(interleave_chip_selects, 1) != 0) {
tom_k = interleave_chip_selects(ctrl); tom_k = interleave_chip_selects(ctrl);
} else { } else {
printk(BIOS_DEBUG, "Interleaving disabled\n"); printk(BIOS_DEBUG, "Interleaving disabled\n");
@ -1530,7 +1530,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
bios_cycle_time = min_cycle_times[ bios_cycle_time = min_cycle_times[
read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)]; read_option(max_mem_clock, 0)];
if (bios_cycle_time > min_cycle_time) { if (bios_cycle_time > min_cycle_time) {
min_cycle_time = bios_cycle_time; min_cycle_time = bios_cycle_time;
} }

6
src/northbridge/amd/amdk8/raminit_f.c
View File

@ -1108,7 +1108,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl,
* and if so count them. * and if so count them.
*/ */
#if defined(CMOS_VSTART_interleave_chip_selects) #if defined(CMOS_VSTART_interleave_chip_selects)
if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) == 0) if (read_option(interleave_chip_selects, 1) == 0)
return 0; return 0;
#else #else
#if !CONFIG_INTERLEAVE_CHIP_SELECTS #if !CONFIG_INTERLEAVE_CHIP_SELECTS
@ -1806,7 +1806,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
bios_cycle_time = min_cycle_times[ bios_cycle_time = min_cycle_times[
#ifdef CMOS_VSTART_max_mem_clock #ifdef CMOS_VSTART_max_mem_clock
read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0) read_option(max_mem_clock, 0)
#else #else
#if defined(CONFIG_MAX_MEM_CLOCK) #if defined(CONFIG_MAX_MEM_CLOCK)
CONFIG_MAX_MEM_CLOCK CONFIG_MAX_MEM_CLOCK
@ -2375,7 +2375,7 @@ static void set_ecc(const struct mem_controller *ctrl,
dcl |= DCL_DimmEccEn; dcl |= DCL_DimmEccEn;
} }
#ifdef CMOS_VSTART_ECC_memory #ifdef CMOS_VSTART_ECC_memory
if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { if (read_option(ECC_memory, 1) == 0) {
dcl &= ~DCL_DimmEccEn; dcl &= ~DCL_DimmEccEn;
} }
#else // CMOS_VSTART_ECC_memory not defined #else // CMOS_VSTART_ECC_memory not defined

2
src/northbridge/intel/e7520/raminit.c
View File

@ -618,7 +618,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
} }
ecc = 2; ecc = 2;
#if CONFIG_HAVE_OPTION_TABLE #if CONFIG_HAVE_OPTION_TABLE
if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { if (read_option(ECC_memory, 1) == 0) {
ecc = 0; /* ECC off in CMOS so disable it */ ecc = 0; /* ECC off in CMOS so disable it */
print_debug("ECC off\n"); print_debug("ECC off\n");
} else } else

2
src/northbridge/intel/e7525/raminit.c
View File

@ -624,7 +624,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
} }
ecc = 2; ecc = 2;
#if CONFIG_HAVE_OPTION_TABLE #if CONFIG_HAVE_OPTION_TABLE
if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) { if (read_option(ECC_memory, 1) == 0) {
ecc = 0; /* ECC off in CMOS so disable it */ ecc = 0; /* ECC off in CMOS so disable it */
print_debug("ECC off\n"); print_debug("ECC off\n");
} else } else

2
src/pc80/mc146818rtc_early.c
View File

@ -92,7 +92,7 @@ static inline int do_normal_boot(void)
return (byte & (1<<1)); return (byte & (1<<1));
} }
unsigned read_option(unsigned start, unsigned size, unsigned def) unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def)
{ {
#if CONFIG_USE_OPTION_TABLE #if CONFIG_USE_OPTION_TABLE
unsigned byte; unsigned byte;