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mainboard/asus/kcma-d8: Add initial ASUS KCMA-D8 support 

Change-Id: Idefa304a27823c741fab72ff5c2f20fed1aa5a39
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13523
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Timothy Pearson 2015-11-24 14:17:49 -06:00 committed by Martin Roth
parent 4551b68c83
commit b251a50714
7 changed files with 77 additions and 161 deletions
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1
src/mainboard/asus/kcma-d8/cmos.default
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@ -23,7 +23,6 @@ sata_alpm = Disable
maximum_p_state_limit = 0xf maximum_p_state_limit = 0xf
probe_filter = Auto probe_filter = Auto
l3_cache_partitioning = Disable l3_cache_partitioning = Disable
ieee1394_controller = Enable
gart = Enable gart = Enable
experimental_memory_speed_boost = Disable experimental_memory_speed_boost = Disable
power_on_after_fail = On power_on_after_fail = On

1
src/mainboard/asus/kcma-d8/cmos.layout
View File

@ -46,7 +46,6 @@ entries
473 2 e 13 dimm_spd_checksum 473 2 e 13 dimm_spd_checksum
475 1 e 14 probe_filter 475 1 e 14 probe_filter
476 1 e 1 l3_cache_partitioning 476 1 e 1 l3_cache_partitioning
477 1 e 1 ieee1394_controller
478 1 e 1 iommu 478 1 e 1 iommu
479 1 e 1 cpu_core_boost 479 1 e 1 cpu_core_boost
480 1 e 1 experimental_memory_speed_boost 480 1 e 1 experimental_memory_speed_boost

40
src/mainboard/asus/kcma-d8/devicetree.cb
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@ -7,11 +7,10 @@ chip northbridge/amd/amdfam10/root_complex # Root complex
device domain 0 on # PCI domain device domain 0 on # PCI domain
subsystemid 0x1043 0x8163 inherit subsystemid 0x1043 0x8163 inherit
chip northbridge/amd/amdfam10 # Northbridge / RAM controller chip northbridge/amd/amdfam10 # Northbridge / RAM controller
register "maximum_memory_capacity" = "0x4000000000" # 256GB register "maximum_memory_capacity" = "0x2000000000" # 128GB
device pci 18.0 on end # Link 0 == LDT 0 device pci 18.0 on end # Link 0 == LDT 0
device pci 18.0 on end # Link 1 == LDT 1 device pci 18.0 on end # Link 1 == LDT 1
device pci 18.0 on end # Link 2 == LDT 2 device pci 18.0 on # Link 2 == LDT 2 [SB on link 2]
device pci 18.0 on # Link 3 == LDT 3 [SB on link 3]
chip southbridge/amd/sr5650 # Primary southbridge chip southbridge/amd/sr5650 # Primary southbridge
device pci 0.0 on end # HT Root Complex 0x9600 device pci 0.0 on end # HT Root Complex 0x9600
device pci 0.1 on end # CLKCONFIG device pci 0.1 on end # CLKCONFIG
@ -36,16 +35,10 @@ chip northbridge/amd/amdfam10/root_complex # Root complex
device pci b.0 on # Bridge (GPP2 Port0) device pci b.0 on # Bridge (GPP2 Port0)
# Slot # PCI E 4 # Slot # PCI E 4
end end
device pci c.0 on # Bridge (GPP2 Port1)
# Slot # PCI E 5
end
device pci d.0 on # Bridge (GPP3b Port0)
# Slot # PCI E 3
end
register "gpp1_configuration" = "0" # Configuration 16:0 default register "gpp1_configuration" = "0" # Configuration 16:0 default
register "gpp2_configuration" = "1" # Configuration 8:8 register "gpp2_configuration" = "1" # Configuration 8:8
register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0 register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0
register "port_enable" = "0x3f1c" # Enable all ports except 0, 1, 5, 6, and 7 register "port_enable" = "0x0f1c" # Enable all ports except 0, 1, 5, 6, and 7
register "pcie_settling_time" = "1000000" # Allow PIKE to be detected / configured register "pcie_settling_time" = "1000000" # Allow PIKE to be detected / configured
end end
chip southbridge/amd/sb700 # Secondary southbridge chip southbridge/amd/sb700 # Secondary southbridge
@ -150,7 +143,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex
register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V
register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V
register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V
register "vsen7_high_limit_mv" = "1250" # VSEN7 (Northbridge core voltage) high limit to 1.25V register "vsen7_high_limit_mv" = "1150" # VSEN7 (Northbridge core voltage) high limit to 1.15V
register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V
register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V
register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V
@ -216,11 +209,16 @@ chip northbridge/amd/amdfam10/root_complex # Root complex
end end
end end
device pci 14.4 on # Bridge device pci 14.4 on # Bridge
device pci 1.0 on end # VGA device pci 1.0 on # Slot
device pci 2.0 on end # FireWire
device pci 3.0 on # Slot
# Slot # PCI 0 # Slot # PCI 0
end end
device pci 2.0 on # Slot
# Slot # PCI 1
end
device pci 3.0 on # Slot
# Slot # PCI 2
end
device pci 5.0 on end # VGA
end end
device pci 14.5 on end # USB OHCI2 0x4399 device pci 14.5 on end # USB OHCI2 0x4399
end end
@ -230,24 +228,12 @@ chip northbridge/amd/amdfam10/root_complex # Root complex
device pci 18.3 on end device pci 18.3 on end
device pci 18.4 on end device pci 18.4 on end
device pci 18.5 on end device pci 18.5 on end
device pci 19.0 on end # Socket 0 node 1 device pci 19.0 on end # Socket 1 node 0
device pci 19.1 on end device pci 19.1 on end
device pci 19.2 on end device pci 19.2 on end
device pci 19.3 on end device pci 19.3 on end
device pci 19.4 on end device pci 19.4 on end
device pci 19.5 on end device pci 19.5 on end
device pci 1a.0 on end # Socket 1 node 0
device pci 1a.1 on end
device pci 1a.2 on end
device pci 1a.3 on end
device pci 1a.4 on end
device pci 1a.5 on end
device pci 1b.0 on end # Socket 1 node 1
device pci 1b.1 on end
device pci 1b.2 on end
device pci 1b.3 on end
device pci 1b.4 on end
device pci 1b.5 on end
end end
end end
end end

92
src/mainboard/asus/kcma-d8/dsdt.asl
View File

@ -1,7 +1,7 @@
/* /*
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2015 Raptor Engineering
* Copyright (C) 2005 - 2012 Advanced Micro Devices, Inc. * Copyright (C) 2005 - 2012 Advanced Micro Devices, Inc.
* Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com> * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
@ -116,8 +116,6 @@ DefinitionBlock (
Notify (\_SB.PCI0.NICA, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify (\_SB.PCI0.NICA, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify (\_SB.PCI0.NICB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify (\_SB.PCI0.NICB, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify (\_SB.PCI0.PCE4, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify (\_SB.PCI0.PCE4, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify (\_SB.PCI0.PCE5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify (\_SB.PCI0.PCE3, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */
@ -125,13 +123,13 @@ DefinitionBlock (
/* Root of the bus hierarchy */ /* Root of the bus hierarchy */
Scope (\_SB) Scope (\_SB)
{ {
/* Top southbridge PCI device (SR5690 + SP5100) */ /* Top southbridge PCI device (SR5670 + SP5100) */
Device (PCI0) Device (PCI0)
{ {
/* BUS0 root bus */ /* BUS0 root bus */
Name (_HID, EisaId ("PNP0A08")) /* PCI-e root bus (SR5690) */ Name (_HID, EisaId ("PNP0A08")) /* PCI-e root bus (SR5670) */
Name (_CID, EisaId ("PNP0A03")) /* PCI root bus (SP5100) */ Name (_CID, EisaId ("PNP0A03")) /* PCI root bus (SP5100) */
Name (_ADR, 0x00180001) Name (_ADR, 0x00180001)
Name (_UID, 0x00) Name (_UID, 0x00)
@ -162,7 +160,7 @@ DefinitionBlock (
/* PCI Routing Tables */ /* PCI Routing Tables */
Name (PR00, Package () { Name (PR00, Package () {
/* PIC */ /* PIC */
/* Top southbridge device (SR5690) */ /* Top southbridge device (SR5670) */
/* HT Link */ /* HT Link */
Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 },
@ -178,12 +176,6 @@ DefinitionBlock (
/* PCI-E Slot 4 (Bridge) */ /* PCI-E Slot 4 (Bridge) */
Package (0x04) { 0x000BFFFF, 0x00, LNKG, 0x00 }, Package (0x04) { 0x000BFFFF, 0x00, LNKG, 0x00 },
/* PCI-E Slot 5 (Bridge) */
Package (0x04) { 0x000CFFFF, 0x00, LNKG, 0x00 },
/* PCI-E Slot 3 (Bridge) */
Package (0x04) { 0x000DFFFF, 0x00, LNKG, 0x00 },
/* Bottom southbridge device (SP5100) */ /* Bottom southbridge device (SP5100) */
/* SATA 0 */ /* SATA 0 */
Package (0x04) { 0x0011FFFF, 0x00, LNKG, 0x00 }, Package (0x04) { 0x0011FFFF, 0x00, LNKG, 0x00 },
@ -200,7 +192,7 @@ DefinitionBlock (
Package (0x04) { 0x0013FFFF, 0x02, LNKA, 0x00 }, Package (0x04) { 0x0013FFFF, 0x02, LNKA, 0x00 },
Package (0x04) { 0x0013FFFF, 0x03, LNKB, 0x00 }, Package (0x04) { 0x0013FFFF, 0x03, LNKB, 0x00 },
/* SMBUS / IDE / LPC / VGA / FireWire / PCI Slot 0 */ /* SMBUS / IDE / LPC / VGA / PCI Slots 0 - 2 */
Package (0x04) { 0x0014FFFF, 0x00, LNKA, 0x00 }, Package (0x04) { 0x0014FFFF, 0x00, LNKA, 0x00 },
Package (0x04) { 0x0014FFFF, 0x01, LNKB, 0x00 }, Package (0x04) { 0x0014FFFF, 0x01, LNKB, 0x00 },
Package (0x04) { 0x0014FFFF, 0x02, LNKC, 0x00 }, Package (0x04) { 0x0014FFFF, 0x02, LNKC, 0x00 },
@ -209,7 +201,7 @@ DefinitionBlock (
Name (AR00, Package () { Name (AR00, Package () {
/* APIC */ /* APIC */
/* Top southbridge device (SR5690) */ /* Top southbridge device (SR5670) */
/* HT Link */ /* HT Link */
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 55 }, Package (0x04) { 0x0000FFFF, 0x00, 0x00, 55 },
@ -225,12 +217,6 @@ DefinitionBlock (
/* PCI-E Slot 4 (Bridge) */ /* PCI-E Slot 4 (Bridge) */
Package (0x04) { 0x000BFFFF, 0x00, 0x00, 54 }, Package (0x04) { 0x000BFFFF, 0x00, 0x00, 54 },
/* PCI-E Slot 5 (Bridge) */
Package (0x04) { 0x000CFFFF, 0x00, 0x00, 54 },
/* PCI-E Slot 3 (Bridge) */
Package (0x04) { 0x000DFFFF, 0x00, 0x00, 54 },
/* Bottom southbridge device (SP5100) */ /* Bottom southbridge device (SP5100) */
/* SATA 0 */ /* SATA 0 */
Package (0x04) { 0x0011FFFF, 0x00, 0x00, 22 }, Package (0x04) { 0x0011FFFF, 0x00, 0x00, 22 },
@ -247,7 +233,7 @@ DefinitionBlock (
Package (0x04) { 0x0013FFFF, 0x02, 0x00, 16 }, Package (0x04) { 0x0013FFFF, 0x02, 0x00, 16 },
Package (0x04) { 0x0013FFFF, 0x03, 0x00, 17 }, Package (0x04) { 0x0013FFFF, 0x03, 0x00, 17 },
/* SMBUS / IDE / LPC / VGA / FireWire / PCI Slot 0 */ /* SMBUS / IDE / LPC / VGA / PCI Slots 0 - 2 */
Package (0x04) { 0x0014FFFF, 0x00, 0x00, 16 }, Package (0x04) { 0x0014FFFF, 0x00, 0x00, 16 },
Package (0x04) { 0x0014FFFF, 0x01, 0x00, 17 }, Package (0x04) { 0x0014FFFF, 0x01, 0x00, 17 },
Package (0x04) { 0x0014FFFF, 0x02, 0x00, 18 }, Package (0x04) { 0x0014FFFF, 0x02, 0x00, 18 },
@ -256,22 +242,36 @@ DefinitionBlock (
Name (PR01, Package () { Name (PR01, Package () {
/* PIC */ /* PIC */
Package (0x04) { 0x1FFFF, 0x00, LNKF, 0x00 }, Package (0x04) { 0x1FFFF, 0x00, LNKE, 0x00 },
Package (0x04) { 0x2FFFF, 0x00, LNKE, 0x00 }, Package (0x04) { 0x1FFFF, 0x01, LNKF, 0x00 },
Package (0x04) { 0x1FFFF, 0x02, LNKG, 0x00 },
Package (0x04) { 0x1FFFF, 0x03, LNKH, 0x00 },
Package (0x04) { 0x2FFFF, 0x00, LNKF, 0x00 },
Package (0x04) { 0x2FFFF, 0x01, LNKG, 0x00 },
Package (0x04) { 0x2FFFF, 0x02, LNKH, 0x00 },
Package (0x04) { 0x2FFFF, 0x03, LNKE, 0x00 },
Package (0x04) { 0x3FFFF, 0x00, LNKG, 0x00 }, Package (0x04) { 0x3FFFF, 0x00, LNKG, 0x00 },
Package (0x04) { 0x3FFFF, 0x01, LNKH, 0x00 }, Package (0x04) { 0x3FFFF, 0x01, LNKH, 0x00 },
Package (0x04) { 0x3FFFF, 0x02, LNKE, 0x00 }, Package (0x04) { 0x3FFFF, 0x02, LNKE, 0x00 },
Package (0x04) { 0x3FFFF, 0x03, LNKF, 0x00 }, Package (0x04) { 0x3FFFF, 0x03, LNKF, 0x00 },
Package (0x04) { 0x5FFFF, 0x00, LNKH, 0x00 },
}) })
Name (AR01, Package () { Name (AR01, Package () {
/* APIC */ /* APIC */
Package (0x04) { 0x1FFFF, 0x00, 0x00, 21 }, Package (0x04) { 0x1FFFF, 0x00, 0x00, 20 },
Package (0x04) { 0x2FFFF, 0x00, 0x00, 20 }, Package (0x04) { 0x1FFFF, 0x01, 0x00, 21 },
Package (0x04) { 0x1FFFF, 0x02, 0x00, 22 },
Package (0x04) { 0x1FFFF, 0x03, 0x00, 23 },
Package (0x04) { 0x2FFFF, 0x00, 0x00, 21 },
Package (0x04) { 0x2FFFF, 0x01, 0x00, 22 },
Package (0x04) { 0x2FFFF, 0x02, 0x00, 23 },
Package (0x04) { 0x2FFFF, 0x03, 0x00, 20 },
Package (0x04) { 0x3FFFF, 0x00, 0x00, 22 }, Package (0x04) { 0x3FFFF, 0x00, 0x00, 22 },
Package (0x04) { 0x3FFFF, 0x01, 0x00, 23 }, Package (0x04) { 0x3FFFF, 0x01, 0x00, 23 },
Package (0x04) { 0x3FFFF, 0x02, 0x00, 20 }, Package (0x04) { 0x3FFFF, 0x02, 0x00, 20 },
Package (0x04) { 0x3FFFF, 0x03, 0x00, 21 }, Package (0x04) { 0x3FFFF, 0x03, 0x00, 21 },
Package (0x04) { 0x5FFFF, 0x00, 0x00, 23 },
}) })
Name (PR02, Package () { Name (PR02, Package () {
@ -734,46 +734,6 @@ DefinitionBlock (
Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
} }
} }
/* 6:00.0 PCIe x16 */
Device (PCE5)
{
Name (_ADR, 0x000C0000) // _ADR: Address
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
{
If (PICM) {
Return (AR07)
} Else {
Return (PR07)
}
}
Device (SLT1)
{
Name (_ADR, 0xFFFF) // _ADR: Address
Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
}
}
/* 7:00.0 PCIe x16 */
Device (PCE3)
{
Name (_ADR, 0x000D0000) // _ADR: Address
Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
{
If (PICM) {
Return (AR08)
} Else {
Return (PR08)
}
}
Device (SLT1)
{
Name (_ADR, 0xFFFF) // _ADR: Address
Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
}
}
} }
Device (PWRB) { /* Start Power button device */ Device (PWRB) { /* Start Power button device */

34
src/mainboard/asus/kcma-d8/mptable.c
View File

@ -132,7 +132,6 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((10)<<2)|(0)), apicid_sr5650, 30); /* Device 10 (LNKG, APIC pin 30) */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((10)<<2)|(0)), apicid_sr5650, 30); /* Device 10 (LNKG, APIC pin 30) */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((11)<<2)|(0)), apicid_sr5650, 30); /* Device 11 (LNKG, APIC pin 30) */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((11)<<2)|(0)), apicid_sr5650, 30); /* Device 11 (LNKG, APIC pin 30) */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30); /* Device 12 (LNKG, APIC pin 30) */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30); /* Device 12 (LNKG, APIC pin 30) */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 30); /* Device 13 (LNKG, APIC pin 30)) */
dev = dev_find_slot(0, PCI_DEVFN(0x2, 0)); dev = dev_find_slot(0, PCI_DEVFN(0x2, 0));
if (dev && dev->enabled) { if (dev && dev->enabled) {
@ -164,11 +163,6 @@ static void *smp_write_config_table(void *v)
uint8_t bus_pci = dev->link_list->secondary; uint8_t bus_pci = dev->link_list->secondary;
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xc)|(0)), apicid_sr5650, 0); /* card behind dev12 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xc)|(0)), apicid_sr5650, 0); /* card behind dev12 */
} }
dev = dev_find_slot(0, PCI_DEVFN(0xd, 0));
if (dev && dev->enabled) {
uint8_t bus_pci = dev->link_list->secondary;
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xd)|(0)), apicid_sr5650, 0); /* card behind dev13 */
}
/* PCI interrupts are level triggered, and are /* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple. * associated with a specific bus/device/function tuple.
@ -195,23 +189,29 @@ static void *smp_write_config_table(void *v)
if (dev && dev->enabled) { if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary; u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */ /* PCI_SLOT 0 */
PCI_INT(bus_pci, 0x1, 0x0, 0x15); PCI_INT(bus_pci, 0x1, 0x0, 0x14);
PCI_INT(bus_pci, 0x1, 0x1, 0x16); PCI_INT(bus_pci, 0x1, 0x1, 0x15);
PCI_INT(bus_pci, 0x1, 0x2, 0x17); PCI_INT(bus_pci, 0x1, 0x2, 0x16);
PCI_INT(bus_pci, 0x1, 0x3, 0x14); PCI_INT(bus_pci, 0x1, 0x3, 0x17);
/* PCI_SLOT 1. */ /* PCI_SLOT 1 */
PCI_INT(bus_pci, 0x2, 0x0, 0x14); PCI_INT(bus_pci, 0x2, 0x0, 0x15);
PCI_INT(bus_pci, 0x2, 0x1, 0x15); PCI_INT(bus_pci, 0x2, 0x1, 0x16);
PCI_INT(bus_pci, 0x2, 0x2, 0x16); PCI_INT(bus_pci, 0x2, 0x2, 0x17);
PCI_INT(bus_pci, 0x2, 0x3, 0x17); PCI_INT(bus_pci, 0x2, 0x3, 0x14);
/* PCI_SLOT 2. */ /* PCI_SLOT 2 */
PCI_INT(bus_pci, 0x3, 0x0, 0x16); PCI_INT(bus_pci, 0x3, 0x0, 0x16);
PCI_INT(bus_pci, 0x3, 0x1, 0x17); PCI_INT(bus_pci, 0x3, 0x1, 0x17);
PCI_INT(bus_pci, 0x3, 0x2, 0x14); PCI_INT(bus_pci, 0x3, 0x2, 0x14);
PCI_INT(bus_pci, 0x3, 0x3, 0x15); PCI_INT(bus_pci, 0x3, 0x3, 0x15);
/* VGA */
PCI_INT(bus_pci, 0x5, 0x0, 0x17);
PCI_INT(bus_pci, 0x5, 0x1, 0x14);
PCI_INT(bus_pci, 0x5, 0x2, 0x15);
PCI_INT(bus_pci, 0x5, 0x3, 0x16);
} }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */

8
src/mainboard/asus/kcma-d8/resourcemap.c
View File

@ -196,7 +196,7 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n * This field defines the end of PCI I/O region n
* [31:25] Reserved * [31:25] Reserved
*/ */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> AMD SR5690 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of cpu 0 --> AMD SR5690 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@ -267,7 +267,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i * [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i * This field defines the highest bus number in configuration region i
*/ */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> AMD SR5690 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of cpu 0 --> AMD SR5690 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
@ -451,7 +451,7 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n * This field defines the end of PCI I/O region n
* [31:25] Reserved * [31:25] Reserved
*/ */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff110, /* link 3 of cpu 0 --> AMD SR5690 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of cpu 0 --> AMD SR5690 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@ -522,7 +522,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i * [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i * This field defines the highest bus number in configuration region i
*/ */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000303, /* link 3 of cpu 0 --> AMD SR5690 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of cpu 0 --> AMD SR5690 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,

62
src/mainboard/asus/kcma-d8/romstage.c
View File

@ -96,28 +96,26 @@ static void switch_spd_mux(uint8_t channel)
static const uint8_t spd_addr_fam15[] = { static const uint8_t spd_addr_fam15[] = {
// Socket 0 Node 0 ("Node 0") // Socket 0 Node 0 ("Node 0")
RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
// Socket 0 Node 1 ("Node 1") // Socket 1 Node 0 ("Node 1")
RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0,
// Socket 1 Node 0 ("Node 2")
RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
// Socket 1 Node 1 ("Node 3")
RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0,
}; };
static const uint8_t spd_addr_fam10[] = { static const uint8_t spd_addr_fam10[] = {
// Socket 0 Node 0 ("Node 0") // Socket 0 Node 0 ("Node 0")
RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
// Socket 0 Node 1 ("Node 1") // Socket 1 Node 0 ("Node 1")
RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0,
// Socket 1 Node 1 ("Node 2")
RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0,
// Socket 1 Node 0 ("Node 3")
RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
}; };
static void activate_spd_rom(const struct mem_controller *ctrl) { static void activate_spd_rom(const struct mem_controller *ctrl) {
/* Nothing needs to be done as there is no SPD mux on this board */
printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id);
if (ctrl->node_id == 0) {
printk(BIOS_DEBUG, "enable_spd_node0()\n");
switch_spd_mux(0x2);
} else if (ctrl->node_id == 1) {
printk(BIOS_DEBUG, "enable_spd_node1()\n");
switch_spd_mux(0x3);
}
} }
/* Voltages are specified by index /* Voltages are specified by index
@ -189,13 +187,12 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat,
} }
for (node = 0; node < MAX_NODES_SUPPORTED; node++) { for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
socket = node / 2; socket = node;
struct DCTStatStruc *pDCTstat; struct DCTStatStruc *pDCTstat;
pDCTstat = pDCTstatA + node; pDCTstat = pDCTstatA + node;
/* reset socket_allowed_voltages before processing each socket */ /* reset socket_allowed_voltages before processing each socket */
if (!(node % 2)) socket_allowed_voltages = allowed_voltages;
socket_allowed_voltages = allowed_voltages;
if (pDCTstat->NodePresent) { if (pDCTstat->NodePresent) {
for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) {
@ -203,10 +200,7 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat,
socket_allowed_voltages &= pDCTstat->DimmSupportedVoltages[dimm]; socket_allowed_voltages &= pDCTstat->DimmSupportedVoltages[dimm];
} }
} }
}
/* set voltage per socket after processing last contained node */
if (pDCTstat->NodePresent && (node % 2)) {
/* Set voltages */ /* Set voltages */
if (socket_allowed_voltages & 0x8) { if (socket_allowed_voltages & 0x8) {
set_voltage = 0x8; set_voltage = 0x8;
@ -223,16 +217,8 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat,
} }
/* Save final DIMM voltages for MCT and SMBIOS use */ /* Save final DIMM voltages for MCT and SMBIOS use */
if (pDCTstat->NodePresent) { for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) {
for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage;
pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage;
}
}
pDCTstat = pDCTstatA + (node - 1);
if (pDCTstat->NodePresent) {
for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) {
pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage;
}
} }
} }
} }
@ -243,23 +229,10 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat,
static void set_peripheral_control_lines(void) { static void set_peripheral_control_lines(void) {
uint8_t byte; uint8_t byte;
uint8_t nvram;
uint8_t enable_ieee1394;
enable_ieee1394 = 1; /* Enable PCICLK5 */
outb(0x41, 0xcd6);
if (get_option(&nvram, "ieee1394_controller") == CB_SUCCESS) outb(0x02, 0xcd7);
enable_ieee1394 = nvram & 0x1;
if (enable_ieee1394) {
/* Enable PCICLK5 (onboard FireWire device) */
outb(0x41, 0xcd6);
outb(0x02, 0xcd7);
} else {
/* Disable PCICLK5 (onboard FireWire device) */
outb(0x41, 0xcd6);
outb(0x00, 0xcd7);
}
/* Enable the RTC AltCentury register */ /* Enable the RTC AltCentury register */
outb(0x41, 0xcd6); outb(0x41, 0xcd6);
@ -584,8 +557,7 @@ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
{ {
/* Force BUID to 0 */ /* Force BUID to 0 */
static const u8 swaplist[] = {0, 0, 0xFF, 0, 0xFF}; static const u8 swaplist[] = {0, 0, 0xFF, 0, 0xFF};
if ((is_fam15h() && (node == 0) && (link == 1)) /* Family 15h BSP SB link */ if ((node == 0) && (link == 2)) { /* BSP SB link */
|| (!is_fam15h() && (node == 0) && (link == 3))) { /* Family 10h BSP SB link */
*List = swaplist; *List = swaplist;
return 1; return 1;
} }