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soc/amd/*/include/data_fabric: rename D18F0_DRAM_* to DF_DRAM_* 

Now that the data fabric PCI device functions are included in the
register definitions, the remaining data fabric device function numbers
can be dropped from the define names.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1a26402b8078d288a7e32c1668591d001fa3ede9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76889
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2023-08-03 00:57:44 +02:00
parent 382c83e6db
commit b25bf3458b
2 changed files with 6 additions and 6 deletions
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2
src/soc/amd/picasso/agesa_acpi.c
View File

@ -85,7 +85,7 @@ static unsigned long gen_crat_memory_entries(struct acpi_crat_header *crat,
} }
if (dram_base_reg & DRAM_BASE_HOLE_EN) { if (dram_base_reg & DRAM_BASE_HOLE_EN) {
dram_hole_ctl = data_fabric_read32(D18F0_DRAM_HOLE_CTL, dram_hole_ctl = data_fabric_read32(DF_DRAM_HOLE_CTL,
IOMS0_FABRIC_ID); IOMS0_FABRIC_ID);
hole_base = (dram_hole_ctl & DRAM_HOLE_CTL_BASE); hole_base = (dram_hole_ctl & DRAM_HOLE_CTL_BASE);
size_below_hole = hole_base - memory_base; size_below_hole = hole_base - memory_base;

10
src/soc/amd/picasso/include/soc/data_fabric.h
View File

@ -50,12 +50,12 @@ union df_ficaa {
#define D18F0_VGAEN DF_REG_ID(0, 0x80) #define D18F0_VGAEN DF_REG_ID(0, 0x80)
#define VGA_ADDR_ENABLE BIT(0) #define VGA_ADDR_ENABLE BIT(0)
#define D18F0_DRAM_HOLE_CTL DF_REG_ID(0, 0x104) #define DF_DRAM_HOLE_CTL DF_REG_ID(0, 0x104)
#define DRAM_HOLE_CTL_VALID BIT(0) #define DRAM_HOLE_CTL_VALID BIT(0)
#define DRAM_HOLE_CTL_BASE_SHFT 24 #define DRAM_HOLE_CTL_BASE_SHFT 24
#define DRAM_HOLE_CTL_BASE (0xff << DRAM_HOLE_CTL_BASE_SHFT) #define DRAM_HOLE_CTL_BASE (0xff << DRAM_HOLE_CTL_BASE_SHFT)
#define D18F0_DRAM_BASE0 DF_REG_ID(0, 0x110) #define DF_DRAM_BASE0 DF_REG_ID(0, 0x110)
#define DRAM_BASE_REG_VALID BIT(0) #define DRAM_BASE_REG_VALID BIT(0)
#define DRAM_BASE_HOLE_EN BIT(1) #define DRAM_BASE_HOLE_EN BIT(1)
#define DRAM_BASE_INTLV_CH_SHFT 4 #define DRAM_BASE_INTLV_CH_SHFT 4
@ -65,7 +65,7 @@ union df_ficaa {
#define DRAM_BASE_ADDR_SHFT 12 #define DRAM_BASE_ADDR_SHFT 12
#define DRAM_BASE_ADDR (0xfffff << DRAM_BASE_ADDR_SHFT) #define DRAM_BASE_ADDR (0xfffff << DRAM_BASE_ADDR_SHFT)
#define D18F0_DRAM_LIMIT0 DF_REG_ID(0, 0x114) #define DF_DRAM_LIMIT0 DF_REG_ID(0, 0x114)
#define DRAM_LIMIT_DST_ID_SHFT 0 #define DRAM_LIMIT_DST_ID_SHFT 0
#define DRAM_LIMIT_DST_ID (0xff << DRAM_LIMIT_DST_ID_SHFT) #define DRAM_LIMIT_DST_ID (0xff << DRAM_LIMIT_DST_ID_SHFT)
#define DRAM_LIMIT_INTLV_NUM_SOCK_SHFT 8 #define DRAM_LIMIT_INTLV_NUM_SOCK_SHFT 8
@ -78,8 +78,8 @@ union df_ficaa {
#define PICASSO_NUM_DRAM_REG 2 #define PICASSO_NUM_DRAM_REG 2
#define DF_DRAM_BASE(dram_map_pair) ((dram_map_pair) * 2 * sizeof(uint32_t) \ #define DF_DRAM_BASE(dram_map_pair) ((dram_map_pair) * 2 * sizeof(uint32_t) \
+ D18F0_DRAM_BASE0) + DF_DRAM_BASE0)
#define DF_DRAM_LIMIT(dram_map_pair) ((dram_map_pair) * 2 * sizeof(uint32_t) \ #define DF_DRAM_LIMIT(dram_map_pair) ((dram_map_pair) * 2 * sizeof(uint32_t) \
+ D18F0_DRAM_LIMIT0) + DF_DRAM_LIMIT0)
#endif /* AMD_PICASSO_DATA_FABRIC_H */ #endif /* AMD_PICASSO_DATA_FABRIC_H */