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bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3. 

Change-Id: Ica1cc90715c1810668e3f4f7282e5757a5688483
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/8312
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Vladimir Serbinenko 2015-01-31 17:45:50 +01:00
parent e1e11e63af
commit b26156ec65
2 changed files with 9 additions and 0 deletions
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5
src/southbridge/intel/bd82x6x/chip.h
View File

@ -89,6 +89,11 @@ struct southbridge_intel_bd82x6x_config {
int docking_supported;
uint8_t pcie_hotplug_map[8];
/* Ports which can be routed to either EHCI or xHCI. */
uint32_t xhci_switchable_ports;
/* Ports which support SuperSpeed (USB 3.0 additional lanes). */
uint32_t superspeed_capable_ports;
};
#endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */

4
src/southbridge/intel/bd82x6x/usb_xhci.c
View File

@ -29,6 +29,7 @@
static void usb_xhci_init(struct device *dev)
{
u32 reg32;
struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
printk(BIOS_DEBUG, "XHCI: Setting up controller.. ");
@ -37,6 +38,9 @@ static void usb_xhci_init(struct device *dev)
reg32 |= 1;
pci_write_config32(dev, 0x44, reg32);
pci_write_config32(dev, 0xd4, config->xhci_switchable_ports);
pci_write_config32(dev, 0xdc, config->superspeed_capable_ports);
/* Enable clock gating */
reg32 = pci_read_config32(dev, 0x40);
reg32 &= ~((1 << 20) | (1 << 21));