arch/riscv: Don't set up virtual memory
Due to changes in the RISC-V Privileged Architecture specification, Linux can now be started in physical memory and it will setup its own page tables. Thus we can delete most of virtual_memory.c. Change-Id: I4e69d15f8ee540d2f98c342bc4ec0c00fb48def0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Jonathan Neuschäfer
Martin Roth
parent
2764919dfb
commit
b26759d703
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@ -975,14 +975,6 @@ config DEBUG_BOOT_STATE
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Control debugging of the boot state machine. When selected displays
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the state boundaries in ramstage.
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config DEBUG_PRINT_PAGE_TABLES
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bool "Print the page tables after construction"
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default n
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depends on ARCH_RISCV
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help
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After the page tables have been built, print them on the debug
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console.
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config DEBUG_ADA_CODE
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bool "Compile debug code in Ada sources"
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default n
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@ -27,7 +27,6 @@ void arch_prog_run(struct prog *prog)
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if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) {
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printk(BIOS_SPEW, "Config string: '%s'\n", config);
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initVirtualMemory();
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printk(BIOS_SPEW, "OK, let's go\n");
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riscvpayload(config, doit);
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}
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@ -32,36 +32,11 @@
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#include <stdint.h>
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#include <arch/encoding.h>
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#define SUPERPAGE_SIZE ((uintptr_t)(RISCV_PGSIZE << RISCV_PGLEVEL_BITS))
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#define VM_CHOICE VM_SV39
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#define VA_BITS 39
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#define MEGAPAGE_SIZE (SUPERPAGE_SIZE << RISCV_PGLEVEL_BITS)
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#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
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#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
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#define supervisor_paddr_valid(start, length) \
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((uintptr_t)(start) >= current.first_user_vaddr + current.bias \
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&& (uintptr_t)(start) + (length) < mem_size \
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&& (uintptr_t)(start) + (length) >= (uintptr_t)(start))
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typedef uintptr_t pte_t;
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extern pte_t* root_page_table;
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void initVirtualMemory(void);
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size_t pte_ppn(pte_t pte);
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pte_t ptd_create(uintptr_t ppn);
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pte_t pte_create(uintptr_t ppn, int prot, int user);
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void print_page_table(void);
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void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart,
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pte_t *pageTableStart);
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void mstatus_init(void); // need to setup mstatus so we know we have virtual memory
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void flush_tlb(void);
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#define DEFINE_MPRV_READ(name, type, insn) \
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static inline type name(type *p); \
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@ -14,13 +14,9 @@
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* GNU General Public License for more details.
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*/
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#include <arch/barrier.h>
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#include <arch/encoding.h>
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#include <atomic.h>
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#include <console/console.h>
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#include <stdint.h>
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#include <vm.h>
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#include <symbols.h>
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/* Delegate controls which traps are delegated to the payload. If you
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* wish to temporarily disable some or all delegation you can, in a
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@ -38,234 +34,6 @@ static int delegate = 0
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| (1 << CAUSE_USER_ECALL)
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;
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pte_t* root_page_table;
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/* Indent the following text by 2*level spaces */
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static void indent(int level)
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{
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int i;
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for (i = 0; i < level; i++)
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printk(BIOS_DEBUG, " ");
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}
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/*
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* Convert a page table index at a given page table level to a virtual address
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* offset
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*/
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static uintptr_t index_to_virt_addr(int index, int level)
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{
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/*
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* Index is at most RISCV_PGLEVEL_BITS bits wide (not considering the
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* leading zeroes. If level==0, the below expression thus shifts index
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* into the highest bits of a 64-bit number, and then shifts it down
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* with sign extension.
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*
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* If level>0, then the expression should work as expected, without any
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* magic.
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*/
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return ((intptr_t)index)
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<< (64 - RISCV_PGLEVEL_BITS - level * RISCV_PGLEVEL_BITS)
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>> (64 - VA_BITS);
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}
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/* Dump the page table structures to the console -- helper function */
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static void print_page_table_at(pte_t *pt, intptr_t virt_addr, int level)
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{
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int i;
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indent(level);
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printk(BIOS_DEBUG, "Level %d page table at 0x%p\n", level, pt);
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for (i = 0; i < RISCV_PGSIZE / sizeof(pte_t); i++) {
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char urwx[8];
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uintptr_t pointer;
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intptr_t next_virt_addr;
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if (!(pt[i] & PTE_V))
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continue;
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urwx[0] = (pt[i] & PTE_U)? 'u' : '-';
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urwx[1] = (pt[i] & PTE_R)? 'r' : '-';
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urwx[2] = (pt[i] & PTE_W)? 'w' : '-';
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urwx[3] = (pt[i] & PTE_X)? 'x' : '-';
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urwx[4] = '\0';
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next_virt_addr = virt_addr + index_to_virt_addr(i, level);
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pointer = ((uintptr_t)pt[i] >> 10) << RISCV_PGSHIFT;
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indent(level + 1);
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printk(BIOS_DEBUG, "Valid PTE at index %d (0x%016zx -> 0x%zx), ",
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i, (size_t) next_virt_addr, (size_t) pointer);
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if (PTE_TABLE(pt[i]))
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printk(BIOS_DEBUG, "page table\n");
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else
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printk(BIOS_DEBUG, "protections %s\n", urwx);
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if (PTE_TABLE(pt[i])) {
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print_page_table_at((pte_t *)pointer, next_virt_addr, level + 1);
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}
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}
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}
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/* Print the page table structures to the console */
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void print_page_table(void) {
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print_page_table_at((void *)(read_csr(sptbr) << RISCV_PGSHIFT), 0, 0);
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}
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void flush_tlb(void)
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{
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asm volatile("sfence.vm");
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}
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size_t pte_ppn(pte_t pte)
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{
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return pte >> PTE_PPN_SHIFT;
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}
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pte_t ptd_create(uintptr_t ppn)
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{
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return (ppn << PTE_PPN_SHIFT) | PTE_V;
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}
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pte_t pte_create(uintptr_t ppn, int prot, int user)
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{
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pte_t pte = (ppn << PTE_PPN_SHIFT) | PTE_R | PTE_V;
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if (prot & PTE_W)
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pte |= PTE_W;
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if (prot & PTE_X)
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pte |= PTE_X;
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if (user)
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pte |= PTE_U;
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return pte;
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}
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// The current RISCV *physical* address space is this:
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// * 0 - 2 GiB: miscellaneous IO devices
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// * 2 GiB - 4 GiB DRAM
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// We have determined, also, that if code references a physical address
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// not backed by a device, we'll take a fault. In other words, we don't
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// need to finely map the memory-mapped devices as we would on an x86.
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// We can use GiB mappings for the IO space and we will take a trap
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// if we reference hardware that does not exist.
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//
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// The intent of the RISCV designers is that pages be set up in M mode
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// for lower privilege software. They have also told me that they
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// expect, unlike other platforms, that next level software use these
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// page tables. Some kernels (Linux) prefer the old fashioned model,
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// where kernel starts with an identity (ID) map and sets up page tables as
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// it sees fit. Other kernels (harvey) are fine with using whatever
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// firmware sets up. We need to accommodate both. So, we set up the
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// identity map for Linux, but also set up the map for kernels that
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// are more willing to conform to the RISCV model. The map is as
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// follows:
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//
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// ID map: map IO space and all of DRAM 1:1 using 1 GiB PTEs
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// I.e. we use 1 GiB PTEs for 4 GiB.
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// Linux/BSD uses this mapping just enough to replace it.
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//
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// Top 2G map: map the 2 Gib - 4 GiB of physical address space to
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// 0xffffffff_80000000. This will be needed until the GNU toolchain can compile
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// code to run at 0xffffffc000000000, i.e. the start of Sv39.
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//
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// Only Harvey/Plan 9 uses this Mapping, and temporarily.
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//
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// standard RISCV map long term: Map IO space, and all of DRAM, to the *lowest*
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// possible negative address for this implementation,
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// e.g. 0xffffffc000000000 for Sv39 CPUs. For now we can use GiB PTEs.
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//
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// RISCV map for now: map IO space, and all of DRAM, starting at
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// 0xffff_ffc0_0000_0000, i.e. just as for Sv39.
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//
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// It is our intent on Harvey (and eventually Akaros) that we use
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// this map, once the toolchain can correctly support it.
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// We have tested this arrangement and it lets us boot harvey to user mode.
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void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, pte_t *pt)
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{
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// 0xFFF... - 0xFFFFFFFF81000000 - RISCV_PGSIZE
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intptr_t memorySize = 0x7F000000;
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// middle page table
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pte_t* middle_pt = (void*)pt;
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size_t num_middle_pts = 2; // 3 level page table, 39 bit virtual address space for now
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// root page table
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pte_t* root_pt = (void*)middle_pt + num_middle_pts * RISCV_PGSIZE;
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memset(middle_pt, 0, (num_middle_pts + 1) * RISCV_PGSIZE); // 0's out middle_pt and root_pt
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for (size_t i = 0; i < num_middle_pts; i++)
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root_pt[(1<<RISCV_PGLEVEL_BITS)-num_middle_pts+i] = ptd_create(((uintptr_t)middle_pt >> RISCV_PGSHIFT) + i);
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// fill the middle page table
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for (uintptr_t vaddr = virtMemStart, paddr = physMemStart;
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paddr < physMemStart + memorySize;
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vaddr += SUPERPAGE_SIZE, paddr += SUPERPAGE_SIZE) {
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int l2_shift = RISCV_PGLEVEL_BITS + RISCV_PGSHIFT;
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size_t l2_idx = (virtMemStart >> l2_shift) & ((1 << RISCV_PGLEVEL_BITS)-1);
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l2_idx += ((vaddr - virtMemStart) >> l2_shift);
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middle_pt[l2_idx] = pte_create(paddr >> RISCV_PGSHIFT,
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PTE_U|PTE_R|PTE_W|PTE_X, 0);
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}
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// IO space. Identity mapped.
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root_pt[0x000] = pte_create(0x00000000 >> RISCV_PGSHIFT,
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PTE_R | PTE_W, 0);
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root_pt[0x001] = pte_create(0x40000000 >> RISCV_PGSHIFT,
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PTE_R | PTE_W, 0);
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root_pt[0x002] = pte_create(0x80000000 >> RISCV_PGSHIFT,
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PTE_R | PTE_W | PTE_X, 0);
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root_pt[0x003] = pte_create(0xc0000000 >> RISCV_PGSHIFT,
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PTE_R | PTE_W | PTE_X, 0);
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// Negative address space map at 0xffffffc000000000
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root_pt[0x100] = root_pt[0];
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root_pt[0x101] = root_pt[1];
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root_pt[0x102] = root_pt[2];
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root_pt[0x103] = root_pt[3];
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mb();
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root_page_table = root_pt;
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uintptr_t ptbr = ((uintptr_t) root_pt) >> RISCV_PGSHIFT;
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write_csr(sptbr, ptbr);
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}
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void initVirtualMemory(void) {
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uintptr_t ms;
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ms = read_csr(mstatus);
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ms = INSERT_FIELD(ms, MSTATUS_VM, VM_CHOICE);
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write_csr(mstatus, ms);
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ms = read_csr(mstatus);
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if (EXTRACT_FIELD(ms, MSTATUS_VM) != VM_CHOICE) {
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printk(BIOS_DEBUG, "We don't have virtual memory...\n");
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return;
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} else {
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printk(BIOS_DEBUG, "-----------------------------\n");
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printk(BIOS_DEBUG, "Virtual memory status enabled\n");
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printk(BIOS_DEBUG, "-----------------------------\n");
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}
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// TODO: Figure out how to grab this from cbfs
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// N.B. We used to map physical from 0x81000000,
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// but since kernels need to be able to see the page tables
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// created by firmware, we're going to map from start of RAM.
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// All this is subject to change as we learn more. Much
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// about RISCV is still in flux.
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printk(BIOS_DEBUG, "Initializing virtual memory...\n");
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uintptr_t physicalStart = 0x80000000;
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uintptr_t virtualStart = 0xffffffff80000000;
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init_vm(virtualStart, physicalStart, (pte_t *)_pagetables);
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mb();
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flush_tlb();
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#if IS_ENABLED(CONFIG_DEBUG_PRINT_PAGE_TABLES)
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printk(BIOS_DEBUG, "Finished initializing virtual memory, starting walk...\n");
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print_page_table();
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#else
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printk(BIOS_DEBUG, "Finished initializing virtual memory\n");
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#endif
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}
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void mstatus_init(void)
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{
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uintptr_t ms = 0;
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