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soc/intel/cannonlake: Update UPD from device switch 

Some of the FSP silicon UPD entry can be updated base on device switch
in pci device tree, have both static config setting and device tree "on"
and "off" will be redundant.

BUG=N/A
TEST=Build and boot up fine with Whiskey Lake RVP platform.

Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27766
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lijian Zhao 2018-07-31 17:23:32 -07:00 committed by Patrick Georgi
parent 80346d0490
commit b269f873b0
9 changed files with 47 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
View File

@ -21,9 +21,7 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "1"
# Intel Common SoC Config
#+-------------------+---------------------------+

2
src/mainboard/google/zoombini/variants/meowth/devicetree.cb
View File

@ -30,9 +30,7 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "SaGv_Enabled"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "1"
# Intel Common SoC Config
#+-------------------+---------------------------+

2
src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
View File

@ -7,9 +7,7 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"

2
src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
View File

@ -7,9 +7,7 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"

2
src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
View File

@ -7,9 +7,7 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"

2
src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb
View File

@ -7,9 +7,7 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"

4
src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb
View File

@ -6,10 +6,7 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "1"
register "HeciEnabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
@ -30,7 +27,6 @@ chip soc/intel/cannonlake
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
register "SataEnable" = "1"
register "SataSalpSupport" = "1"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"

72
src/soc/intel/cannonlake/chip.c
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016-2017 Intel Corporation.
* Copyright (C) 2016-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -208,16 +208,25 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchLockDownRtcMemoryLock = 0;
/* SATA */
params->SataEnable = config->SataEnable;
params->SataMode = config->SataMode;
params->SataSalpSupport = config->SataSalpSupport;
memcpy(params->SataPortsEnable, config->SataPortsEnable,
dev = dev_find_slot(0, PCH_DEVFN_SATA);
if (!dev)
params->SataEnable = 0;
else {
params->SataEnable = dev->enabled;
params->SataMode = config->SataMode;
params->SataSalpSupport = config->SataSalpSupport;
memcpy(params->SataPortsEnable, config->SataPortsEnable,
sizeof(params->SataPortsEnable));
memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
sizeof(params->SataPortsDevSlp));
}
/* Lan */
params->PchLanEnable = config->PchLanEnable;
dev = dev_find_slot(0, PCH_DEVFN_GBE);
if (!dev)
params->PchLanEnable = 0;
else
params->PchLanEnable = dev->enabled;
/* Audio */
params->PchHdaDspEnable = config->PchHdaDspEnable;
@ -237,18 +246,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* USB */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
params->PortUsb20Enable[i] =
config->usb2_ports[i].enable;
params->Usb2OverCurrentPin[i] =
config->usb2_ports[i].ocpin;
params->Usb2AfePetxiset[i] =
config->usb2_ports[i].pre_emp_bias;
params->Usb2AfeTxiset[i] =
config->usb2_ports[i].tx_bias;
params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias;
params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias;
params->Usb2AfePredeemp[i] =
config->usb2_ports[i].tx_emp_enable;
params->Usb2AfePehalfbit[i] =
config->usb2_ports[i].pre_emp_bit;
params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
}
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
@ -283,16 +287,32 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(config->PcieClkSrcClkReq));
/* eMMC and SD */
params->ScsEmmcEnabled = config->ScsEmmcEnabled;
params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed;
if (config->EmmcHs400DllNeed == 1) {
params->PchScsEmmcHs400RxStrobeDll1 =
config->EmmcHs400RxStrobeDll1;
params->PchScsEmmcHs400TxDataDll = config->EmmcHs400TxDataDll;
dev = dev_find_slot(0, PCH_DEVFN_EMMC);
if (!dev)
params->ScsEmmcEnabled = 0;
else {
params->ScsEmmcEnabled = dev->enabled;
params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed;
if (config->EmmcHs400DllNeed == 1) {
params->PchScsEmmcHs400RxStrobeDll1 =
config->EmmcHs400RxStrobeDll1;
params->PchScsEmmcHs400TxDataDll =
config->EmmcHs400TxDataDll;
}
}
params->ScsSdCardEnabled = config->ScsSdCardEnabled;
params->ScsUfsEnabled = config->ScsUfsEnabled;
dev = dev_find_slot(0, PCH_DEVFN_SDCARD);
if (!dev)
params->ScsSdCardEnabled = 0;
else
params->ScsSdCardEnabled = dev->enabled;
dev = dev_find_slot(0, PCH_DEVFN_UFS);
if (!dev)
params->ScsUfsEnabled = 0;
else
params->ScsUfsEnabled = dev->enabled;
params->Heci3Enabled = config->Heci3Enabled;
params->Device4Enable = config->Device4Enable;

10
src/soc/intel/cannonlake/chip.h
View File

@ -3,7 +3,7 @@
*
* Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2017 Intel Corporation.
* Copyright (C) 2017-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -118,9 +118,6 @@ struct soc_intel_cannonlake_config {
/* Rank Margin Tool. 1:Enable, 0:Disable */
uint8_t RMT;
/* LAN controller. 1:Enable, 0:Disable */
uint8_t PchLanEnable;
/* USB related */
struct usb2_port_config usb2_ports[16];
struct usb3_port_config usb3_ports[10];
@ -130,9 +127,7 @@ struct soc_intel_cannonlake_config {
/* Wake Enable Bitmap for USB3 ports */
uint16_t usb3_wake_enable_bitmap;
/* SATA related */
uint8_t SataEnable;
uint8_t SataMode;
uint8_t SataSalpSupport;
uint8_t SataPortsEnable[8];
@ -168,7 +163,6 @@ struct soc_intel_cannonlake_config {
uint8_t SmbusEnable;
/* eMMC and SD */
uint8_t ScsEmmcEnabled;
uint8_t ScsEmmcHs400Enabled;
/* Need to update DLL setting to get Emmc running at HS400 speed */
uint8_t EmmcHs400DllNeed;
@ -176,8 +170,6 @@ struct soc_intel_cannonlake_config {
uint8_t EmmcHs400RxStrobeDll1;
/* 0-78: number of active delay for TX data, unit is 125 psec */
uint8_t EmmcHs400TxDataDll;
uint8_t ScsSdCardEnabled;
uint8_t ScsUfsEnabled;
/* Integrated Sensor */
uint8_t PchIshEnable;