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soc/intel/skylake: Add proper support to enable UART2 in 16550 mode 

Need to perform a dummy read in order to activate LPSS UART's
16550 8-bit compatibility mode.

TEST=Able to get serial log in both 32 bit and 8 bit mode through
LPSS UART2 based on CONFIG_DRIVERS_UART_8250MEM_32 and
CONFIG_DRIVERS_UART_8250MEM selection.

Change-Id: I5f23fef4522743efd49167afb04d56032e16e417
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik 2017-08-10 13:57:07 +05:30 committed by Aaron Durbin
parent f710955b93
commit b27aa82a50
1 changed files with 10 additions and 5 deletions
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15
src/soc/intel/skylake/bootblock/uart.c
View File

@ -27,9 +27,7 @@
/* Serial IO UART controller legacy mode */
#define PCR_SERIAL_IO_GPPRVRW7 0x618
#define PCR_SIO_PCH_LEGACY_UART0 (1 << 0)
#define PCR_SIO_PCH_LEGACY_UART1 (1 << 1)
#define PCR_SIO_PCH_LEGACY_UART2 (1 << 2)
#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx))
/* UART2 pad configuration. Support RXD and TXD for now. */
static const struct pad_config uart2_pads[] = {
@ -44,9 +42,16 @@ void pch_uart_init(void)
uart_common_init(PCH_DEV_UART2, base);
/* Put UART2 in byte access mode for 16550 compatibility */
if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))
if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) {
pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
PCR_SIO_PCH_LEGACY_UART2);
PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));
/*
* Dummy read after setting any of GPPRVRW7.
* Required for UART 16550 8-bit Legacy mode to become active
*/
lpss_clk_read(base);
}
gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
}