mb/google/volteer: Disable HybridStorageMode for volteer baseboard

HybridStorageMode FSP UPD needs to be set only for optane storage.
Enabling HybridStorageMode causes some extra delay in FspSiliconInit due
to HECI command and hence is avoided for NVMe and SATA scenerios. This
change disables "HybridStorageMode" for volteer baseboard. For boards
using optane HybridStorage needs to be enabled from overwrite devicetree.
We are enabling HybridStorage for volteer and volteer2 as those plaforms
have SKU's with optane storage.

BUG=b:158573805
TEST=Build and boot non optane device and confirm that FspSiliconInit
time is reduced. This saves ~100ms.

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I54fc78e3f888d4f2a02ba0ad6b9aef33eb872a9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/mainboard/google/volteer/variants/baseboard/devicetree.cb

@@ -87,7 +87,7 @@ chip soc/intel/tigerlake
 	# Enable Optane PCIE 11 using clk 0
 	register "PcieRpEnable[10]" = "1"
 	register "PcieRpLtrEnable[10]" = "1"
-	register "HybridStorageMode" = "1"
+	register "HybridStorageMode" = "0"
 
 	# Enable SD Card PCIE 8 using clk 3
 	register "PcieRpEnable[7]" = "1"

src/mainboard/google/volteer/variants/volteer/overridetree.cb

@@ -47,6 +47,8 @@ chip soc/intel/tigerlake
 	register "IomTypeCPortPadCfg[0]" = "0x090E000A"
 	register "IomTypeCPortPadCfg[1]" = "0x090E000D"
 
+	register "HybridStorageMode" = "1"
+
 	device domain 0 on
 		device ref ipu on end
 		device ref i2c0 on

src/mainboard/google/volteer/variants/volteer2/overridetree.cb

@@ -5,6 +5,8 @@ chip soc/intel/tigerlake
 	register "DdiPort1Hpd" = "0"
 	register "DdiPort2Hpd" = "0"
 
+	register "HybridStorageMode" = "1"
+
 	device domain 0 on
 		device ref dptf on
 			chip drivers/intel/dptf