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soc/intel/cmn/block/smm: Clear SPI SYNC_SS before disabling WPD 

This patch follows the BWG recommendation (doc 729123) by clearing
the SPI SYNC_SS bit before disabling the WPD bit in
SPI_BIOS_CONTROL. This prevents boot hangs due to a 3-strike error.

Unable to follow this guideline would result into boot hang
(3-strike error).

BRANCH=firmware-rex-15709.B
TEST=Able to build and boot google/rex.

Change-Id: I18dbbc92554d803eea38ceb0b936a9da9191cb11
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Subrata Banik 2023-12-20 20:36:05 +05:30
parent e9b7623028
commit b27cfd62b2
1 changed files with 6 additions and 2 deletions
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8
src/soc/intel/common/block/smm/smihandler.c
View File

@ -297,9 +297,13 @@ static void southbridge_smi_store(
const bool wp_enabled = !fast_spi_wpd_status();
if (wp_enabled) {
set_insmm_sts(true);
fast_spi_disable_wp();
/* Not clearing SPI sync SMI status here results in hangs */
/*
* As per BWG, clearing "SPI_BIOS_CONTROL_SYNC_SS"
* bit is a must prior setting SPI_BIOS_CONTROL_WPD" bit
* to avoid 3-strike error.
*/
fast_spi_clear_sync_smi_status();
fast_spi_disable_wp();
}
/* drivers/smmstore/smi.c */