southbridge/amd/sb700/acpi: Add IDE / SATA ASL code
Change-Id: I507c93556dd66c3590c8ca11c06cd5b2dd7884c5 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12176 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
This commit is contained in:
Timothy Pearson
Peter Stuge
parent
04cf449e77
commit
b27dfe9998
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Some timing tables */
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Name(UDTT, Package(){ /* Udma timing table */
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120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
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})
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Name(MDTT, Package(){ /* MWDma timing table */
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480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
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})
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Name(POTT, Package(){ /* Pio timing table */
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600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
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})
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/* Some timing register value tables */
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Name(MDRT, Package(){ /* MWDma timing register table */
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0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
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})
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Name(PORT, Package(){
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0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
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})
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OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
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Field(ICRG, AnyAcc, NoLock, Preserve)
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{
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PPTS, 8, /* Primary PIO Slave Timing */
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PPTM, 8, /* Primary PIO Master Timing */
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OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
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PMTM, 8, /* Primary MWDMA Master Timing */
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OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
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OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
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PPSM, 4, /* Primary PIO slave Mode */
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OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
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OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
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PDSM, 4, /* Primary UltraDMA Mode */
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}
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Method(GTTM, 1) /* get total time*/
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{
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Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
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Increment(Local0)
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Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
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Increment(Local1)
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Return(Multiply(30, Add(Local0, Local1)))
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}
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Device(PRID)
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{
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Name (_ADR, Zero)
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Method(_GTM, 0, Serialized)
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{
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NAME(OTBF, Buffer(20) { /* out buffer */
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
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})
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CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
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CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
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CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
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CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
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CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
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/* Just return if the channel is disabled */
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If(And(PPCR, 0x01)) { /* primary PIO control */
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Return(OTBF)
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}
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/* Always tell them independent timing available and IOChannelReady used on both drives */
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Or(BFFG, 0x1A, BFFG)
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Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
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Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
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If(And(PDCR, 0x01)) { /* It's under UDMA mode */
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Or(BFFG, 0x01, BFFG)
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Store(DerefOf(Index(UDTT, PDMM)), DSD0)
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}
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Else {
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Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
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}
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If(And(PDCR, 0x02)) { /* It's under UDMA mode */
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Or(BFFG, 0x04, BFFG)
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Store(DerefOf(Index(UDTT, PDSM)), DSD1)
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}
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Else {
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Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
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}
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Return(OTBF) /* out buffer */
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} /* End Method(_GTM) */
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Method(_STM, 3, Serialized)
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{
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NAME(INBF, Buffer(20) { /* in buffer */
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
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})
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CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
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CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
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CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
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CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
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CreateDwordField(INBF, 16, BFFG) /*buffer flag */
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Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
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Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
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Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
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Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
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Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
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Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
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If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
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Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
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Divide(Local0, 7, PDMM,)
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Or(PDCR, 0x01, PDCR)
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}
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Else {
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If(LNotEqual(DSD0, 0xFFFFFFFF)) {
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Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
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Store(DerefOf(Index(MDRT, Local0)), PMTM)
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}
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}
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If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
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Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
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Divide(Local0, 7, PDSM,)
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Or(PDCR, 0x02, PDCR)
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}
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Else {
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If(LNotEqual(DSD1, 0xFFFFFFFF)) {
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Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
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Store(DerefOf(Index(MDRT, Local0)), PMTS)
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}
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}
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/* Return(INBF) */
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} /*End Method(_STM) */
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Device(MST)
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{
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Name(_ADR, 0)
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Method(_GTF, 0, Serialized) {
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Name(CMBF, Buffer(21) {
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0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
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0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
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})
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CreateByteField(CMBF, 1, POMD)
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CreateByteField(CMBF, 8, DMMD)
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CreateByteField(CMBF, 5, CMDA)
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CreateByteField(CMBF, 12, CMDB)
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CreateByteField(CMBF, 19, CMDC)
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Store(0xA0, CMDA)
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Store(0xA0, CMDB)
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Store(0xA0, CMDC)
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Or(PPMM, 0x08, POMD)
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If(And(PDCR, 0x01)) {
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Or(PDMM, 0x40, DMMD)
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}
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Else {
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Store(Match
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(MDTT, MLE, GTTM(PMTM),
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MTR, 0, 0), Local0)
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If(LLess(Local0, 3)) {
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Or(0x20, Local0, DMMD)
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}
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}
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Return(CMBF)
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}
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} /* End Device(MST) */
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Device(SLAV)
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{
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Name(_ADR, 1)
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Method(_GTF, 0, Serialized) {
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Name(CMBF, Buffer(21) {
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0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
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0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
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})
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CreateByteField(CMBF, 1, POMD)
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CreateByteField(CMBF, 8, DMMD)
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CreateByteField(CMBF, 5, CMDA)
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CreateByteField(CMBF, 12, CMDB)
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CreateByteField(CMBF, 19, CMDC)
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Store(0xB0, CMDA)
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Store(0xB0, CMDB)
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Store(0xB0, CMDC)
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Or(PPSM, 0x08, POMD)
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If(And(PDCR, 0x02)) {
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Or(PDSM, 0x40, DMMD)
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}
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Else {
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Store(Match
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(MDTT, MLE, GTTM(PMTS),
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MTR, 0, 0), Local0)
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If(LLess(Local0, 3)) {
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Or(0x20, Local0, DMMD)
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}
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}
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Return(CMBF)
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}
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} /* End Device(SLAV) */
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}
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@ -0,0 +1,133 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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Name(STTM, Buffer(20) {
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0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
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0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
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0x1f, 0x00, 0x00, 0x00
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})
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/* Start by clearing the PhyRdyChg bits */
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Method(_INI) {
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\_GPE._L1F()
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}
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Device(PMRY)
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{
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Name(_ADR, 0)
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Method(_GTM, 0x0, NotSerialized) {
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Return(STTM)
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}
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Method(_STM, 0x3, NotSerialized) {}
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Device(PMST) {
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Name(_ADR, 0)
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Method(_STA,0) {
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if (LGreater(P0IS,0)) {
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return (0x0F) /* sata is visible */
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} else {
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return (0x00) /* sata is missing */
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}
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}
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}/* end of PMST */
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Device(PSLA)
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{
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Name(_ADR, 1)
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Method(_STA,0) {
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if (LGreater(P1IS,0)) {
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return (0x0F) /* sata is visible */
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} else {
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return (0x00) /* sata is missing */
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}
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}
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} /* end of PSLA */
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} /* end of PMRY */
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Device(SEDY)
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{
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Name(_ADR, 1) /* IDE Scondary Channel */
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Method(_GTM, 0x0, NotSerialized) {
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Return(STTM)
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}
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Method(_STM, 0x3, NotSerialized) {}
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Device(SMST)
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{
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Name(_ADR, 0)
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Method(_STA,0) {
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if (LGreater(P2IS,0)) {
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return (0x0F) /* sata is visible */
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} else {
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return (0x00) /* sata is missing */
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}
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}
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} /* end of SMST */
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Device(SSLA)
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{
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Name(_ADR, 1)
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Method(_STA,0) {
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if (LGreater(P3IS,0)) {
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return (0x0F) /* sata is visible */
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} else {
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return (0x00) /* sata is missing */
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}
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}
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} /* end of SSLA */
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} /* end of SEDY */
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/* SATA Hot Plug Support */
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Scope(\_GPE) {
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Method(_L1F,0x0,NotSerialized) {
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if (\_SB.P0PR) {
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if (LGreater(\_SB.P0IS,0)) {
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sleep(32)
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}
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Notify(\_SB.PCI0.SAT0.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
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store(one, \_SB.P0PR)
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}
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if (\_SB.P1PR) {
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if (LGreater(\_SB.P1IS,0)) {
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sleep(32)
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}
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Notify(\_SB.PCI0.SAT0.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
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store(one, \_SB.P1PR)
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}
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if (\_SB.P2PR) {
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if (LGreater(\_SB.P2IS,0)) {
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sleep(32)
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}
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Notify(\_SB.PCI0.SAT0.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
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store(one, \_SB.P2PR)
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}
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if (\_SB.P3PR) {
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if (LGreater(\_SB.P3IS,0)) {
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sleep(32)
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}
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Notify(\_SB.PCI0.SAT0.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
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store(one, \_SB.P3PR)
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}
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}
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}
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