soc/intel/braswell: Add SMBus support
Intel Braswell SoC contains SMBus controller but no support is available for this controller. This controller is compatible with the Intel SMBus support in the southbridge common directory. To be able using smbus support from the Intel common directory the smbus.c is moved outside SOUTHBRIDGE_INTEL_COMMON dependency block. Use SOUTHBRIDGE_INTEL_COMMON_SMBUS to include support. BUG=N/A TEST= Facebook FBG-1710 LCD panel Change-Id: Ie3d4f657558a1aed21b083ef5cad08ea96e629c3 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -50,6 +50,7 @@ config CPU_SPECIFIC_OPTIONS
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select INTEL_GMA_ACPI
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select INTEL_GMA_SWSMISCI
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select CPU_INTEL_COMMON
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select SOUTHBRIDGE_INTEL_COMMON_SMBUS
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config VBOOT
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select VBOOT_STARTS_IN_ROMSTAGE
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@ -22,6 +22,9 @@ romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
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ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
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postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
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romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
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ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
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ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y)
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romstage-y += pmbase.c
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@ -37,9 +40,6 @@ romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
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ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
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smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
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romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
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ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
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romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c
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postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c
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ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c
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