arch/x86: Flip HAVE_MONOTONIC_TIMER default
Change-Id: Id56139a3d0840684b13179821a77bc8ae28e05ae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -507,7 +507,7 @@ config NO_MONOTONIC_TIMER
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config HAVE_MONOTONIC_TIMER
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bool
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depends on !NO_MONOTONIC_TIMER
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default y if !ARCH_X86
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default y
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help
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The board/chipset provides a monotonic timer.
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@ -7,7 +7,6 @@ config CPU_AMD_MODEL_10XXX
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select SSE2
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select TSC_SYNC_LFENCE
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select UDELAY_LAPIC
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select HAVE_MONOTONIC_TIMER
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select SUPPORT_CPU_UCODE_IN_CBFS
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select CPU_MICROCODE_MULTIPLE_FILES
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select ACPI_HUGE_LOWMEM_BACKUP
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@ -10,7 +10,6 @@ config CPU_SPECIFIC_OPTIONS
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select ARCH_VERSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select HAVE_MONOTONIC_TIMER
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select SMP
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select MMX
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select SSE2
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@ -26,6 +26,7 @@ config SLOT_SPECIFIC_OPTIONS # dummy
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select CPU_INTEL_MODEL_6BX
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select CPU_INTEL_MODEL_6XX
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select NO_SMM
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select NO_MONOTONIC_TIMER
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config DCACHE_RAM_BASE
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hex
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@ -21,5 +21,6 @@ config CPU_QEMU_X86
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select ARCH_RAMSTAGE_X86_32
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select SMP
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select UDELAY_TSC
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select NO_MONOTONIC_TIMER
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select C_ENVIRONMENT_BOOTBLOCK
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select SMM_ASEG
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@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select UDELAY_TSC
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select NO_MONOTONIC_TIMER
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select MMX
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select SSE2
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select SUPPORT_CPU_UCODE_IN_CBFS
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@ -24,7 +24,6 @@ config UDELAY_LAPIC
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config LAPIC_MONOTONIC_TIMER
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def_bool n
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depends on UDELAY_LAPIC
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select HAVE_MONOTONIC_TIMER
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help
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Expose monotonic time using the local APIC.
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@ -45,7 +44,6 @@ config TSC_CONSTANT_RATE
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config TSC_MONOTONIC_TIMER
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def_bool n
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depends on UDELAY_TSC
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select HAVE_MONOTONIC_TIMER
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help
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Expose monotonic time using the TSC.
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@ -34,7 +34,6 @@ config CPU_SPECIFIC_OPTIONS
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select GENERIC_UDELAY
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select IOAPIC
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select HAVE_USBDEBUG_OPTIONS
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select HAVE_MONOTONIC_TIMER
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select SPI_FLASH if HAVE_ACPI_RESUME
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select TSC_SYNC_LFENCE
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select COLLECT_TIMESTAMPS
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@ -39,7 +39,6 @@ config CPU_SPECIFIC_OPTIONS
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select GENERIC_UDELAY
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select IOAPIC
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select HAVE_USBDEBUG_OPTIONS
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select HAVE_MONOTONIC_TIMER
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select SPI_FLASH if HAVE_ACPI_RESUME
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select TSC_SYNC_LFENCE
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select COLLECT_TIMESTAMPS
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@ -101,7 +101,6 @@ config CPU_SPECIFIC_OPTIONS
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select UDELAY_TSC
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select TSC_CONSTANT_RATE
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select TSC_MONOTONIC_TIMER
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select HAVE_MONOTONIC_TIMER
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select PLATFORM_USES_FSP2_0
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select UDK_2015_BINDING if !SOC_INTEL_GLK
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select UDK_2017_BINDING if SOC_INTEL_GLK
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@ -19,7 +19,6 @@ config CPU_SPECIFIC_OPTIONS
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select SUPPORT_CPU_UCODE_IN_CBFS
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select MICROCODE_BLOB_NOT_IN_BLOB_REPO
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select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
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select HAVE_MONOTONIC_TIMER
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select HAVE_SMI_HANDLER
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select NO_FIXED_XIP_ROM_SIZE
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select PARALLEL_MP
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@ -18,7 +18,6 @@ config CPU_SPECIFIC_OPTIONS
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select SUPPORT_CPU_UCODE_IN_CBFS
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select HAVE_MONOTONIC_TIMER
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select HAVE_SMI_HANDLER
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select SOUTHBRIDGE_INTEL_COMMON_RESET
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select HAVE_USBDEBUG
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@ -66,7 +66,6 @@ config CPU_SPECIFIC_OPTIONS
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select GENERIC_GPIO_LIB
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select HAVE_FSP_GOP
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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select HAVE_MONOTONIC_TIMER
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select HAVE_SMI_HANDLER
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select IDT_IN_EVERY_STAGE
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select INTEL_GMA_ACPI
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@ -23,7 +23,6 @@ config CPU_SPECIFIC_OPTIONS
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select GENERIC_GPIO_LIB
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select HAVE_FSP_GOP
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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select HAVE_MONOTONIC_TIMER
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select HAVE_SMI_HANDLER
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select IDT_IN_EVERY_STAGE
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select INTEL_GMA_ACPI
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@ -27,7 +27,6 @@ config CPU_SPECIFIC_OPTIONS
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select ARCH_ROMSTAGE_X86_32
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select ARCH_VERSTAGE_X86_32
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select C_ENVIRONMENT_BOOTBLOCK
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select HAVE_MONOTONIC_TIMER
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select NO_MMCONF_SUPPORT
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select REG_SCRIPT
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select SOC_INTEL_COMMON
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@ -38,7 +38,6 @@ config CPU_SPECIFIC_OPTIONS
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select GENERIC_GPIO_LIB
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select HAVE_FSP_GOP
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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select HAVE_MONOTONIC_TIMER
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select HAVE_SMI_HANDLER
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select INTEL_CAR_NEM_ENHANCED
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select INTEL_GMA_ACPI
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