mb/ocp/deltalake: Config PCH PCIe ports in devicetree

Tested on OCP Delta Lake with lspci checking if PCIe speed is changed
are expected.

Change-Id: I189027c403814d68db2b7c5f41fc254a293fe3a1
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
This commit is contained in:
Morgan Jang 2020-05-25 12:23:59 +08:00 committed by Philipp Deppenwiese
parent b8d0d089b3
commit b29d16fc8a
3 changed files with 46 additions and 0 deletions

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@ -39,6 +39,12 @@ chip soc/intel/xeon_sp/cpx
register "gen1_dec" = "0x00fc0601" # BIC in-band update support register "gen1_dec" = "0x00fc0601" # BIC in-band update support
register "gen2_dec" = "0x000c0ca1" # IPMI KCS register "gen2_dec" = "0x000c0ca1" # IPMI KCS
# configure PCH PCIe port
register "pch_pci_port[8]" = "{
.ForceEnable = 0x1,
.PortLinkSpeed = PcieAuto,
}"
device cpu_cluster 0 on device cpu_cluster 0 on
device lapic 0 on end device lapic 0 on end
end end

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@ -7,6 +7,7 @@
#include <FspmUpd.h> #include <FspmUpd.h>
#include <soc/romstage.h> #include <soc/romstage.h>
#include "chip.h"
#include "ipmi.h" #include "ipmi.h"
#include "vpd.h" #include "vpd.h"
@ -74,7 +75,21 @@ static void mainboard_config_gpios(FSPM_UPD *mupd)
static void mainboard_config_iio(FSPM_UPD *mupd) static void mainboard_config_iio(FSPM_UPD *mupd)
{ {
uint8_t index;
const config_t *config = config_of_soc();
oem_update_iio(mupd); oem_update_iio(mupd);
for (index = 0; index < MAX_PCH_PCIE_PORT; index++) {
mupd->FspmConfig.PchPcieForceEnable[index] =
config->pch_pci_port[index].ForceEnable;
mupd->FspmConfig.PchPciePortLinkSpeed[index] =
config->pch_pci_port[index].PortLinkSpeed;
}
mupd->FspmConfig.PchPcieRootPortFunctionSwap = 0x00;
/* The default value is 0XFF in FSP, set it to 0xFE by platform */
mupd->FspmConfig.PchPciePllSsc = 0xFE;
} }
void mainboard_memory_init_params(FSPM_UPD *mupd) void mainboard_memory_init_params(FSPM_UPD *mupd)

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@ -7,10 +7,35 @@
#include <soc/irq.h> #include <soc/irq.h>
#include <stdint.h> #include <stdint.h>
#define MAX_PCH_PCIE_PORT 20
/**
UPD_PCH_PCIE_PORT:
ForceEnable - Enable/Disable PCH PCIe port
PortLinkSpeed - Port Link Speed. Use PCIE_LINK_SPEED to set
**/
struct pch_pcie_port {
uint8_t ForceEnable;
uint8_t PortLinkSpeed;
};
/**
PCIe Link Speed Selection
**/
typedef enum {
PcieAuto = 0,
PcieGen1,
PcieGen2,
PcieGen3
} pcie_link_speed;
struct soc_intel_xeon_sp_cpx_config { struct soc_intel_xeon_sp_cpx_config {
/* Common struct containing soc config data required by common code */ /* Common struct containing soc config data required by common code */
struct soc_intel_common_config common_soc_config; struct soc_intel_common_config common_soc_config;
/* Struct for configuring PCH PCIe port */
struct pch_pcie_port pch_pci_port[MAX_PCH_PCIE_PORT];
/** /**
* Interrupt Routing configuration * Interrupt Routing configuration
* If bit7 is 1, the interrupt is disabled. * If bit7 is 1, the interrupt is disabled.