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soc/intel/cannonlake: Fix PEG1 _PRT generation 

Some weird things happen inside FSP and the routing is not correctly
applied, with PIN D being used but lacking a proper routing in ACPI.
To work around this issue generate _PRT for all 4 INT pins.

Change-Id: I5be6e4514f8c6a47bb887d9f9b95181c9f426a51
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Arthur Heymans 2021-10-21 10:40:23 +02:00 committed by Felix Held
parent 37e261f374
commit b2a442ed59
1 changed files with 6 additions and 0 deletions
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6
src/soc/intel/cannonlake/fsp_params.c
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@ -44,6 +44,12 @@ static const struct slot_irq_constraints irq_constraints[] = {
FIXED_INT_PIRQ(SA_DEVFN_PEG0, PCI_INT_A, PIRQ_A), FIXED_INT_PIRQ(SA_DEVFN_PEG0, PCI_INT_A, PIRQ_A),
FIXED_INT_PIRQ(SA_DEVFN_PEG1, PCI_INT_B, PIRQ_B), FIXED_INT_PIRQ(SA_DEVFN_PEG1, PCI_INT_B, PIRQ_B),
FIXED_INT_PIRQ(SA_DEVFN_PEG2, PCI_INT_C, PIRQ_C), FIXED_INT_PIRQ(SA_DEVFN_PEG2, PCI_INT_C, PIRQ_C),
/*
* It looks like FSP does not apply this mapping properly to
* the PEG functions. The PINx to PIRQx mapping needs to be there
* in ACPI however in case PIN D is used.
*/
FIXED_INT_PIRQ(PCI_DEVFN(SA_DEV_SLOT_PEG, 3), PCI_INT_D, PIRQ_D),
}, },
}, },
{ {