From b2cddd4c12d99df55a1fd856cceea27372ce3f69 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sun, 5 May 2013 12:09:16 +0200 Subject: [PATCH] ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case Currently the code in the if statement if (!byte) do_smbus_write_byte(0xb20, 0x15, 0x3, byte); only gets executed if `byte == 0x0`, that means only in the default case where RAM voltage is 1.5 Volts. But the RAM voltage should be changed when configured for the non-default case. So negate the predicate to alter the RAM voltage for the non-default cases. To prevent the build error OBJCOPY cbfs/fallback/coreboot_ram.elf coreboot-builds/asus_f2a85-m/generated/crt0.romstage.o: In function `cache_as_ram_main': /srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/mainboard/asus/f2a85-m/romstage.c:106: undefined reference to `do_smbus_write_byte' collect2: error: ld returned 1 exit status make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/romstage_null.debug] Error 1 add `southbridge/amd/agesa/hudson/smbus.c` providing the function `do_smbus_write_byte` to ROM stage in `Makefile.inc`. That can actually be used after the needed header files are included in a previous commit. Change-Id: I89542479c4cf6d412614bcf4586ea98e097328d6 Reported-by: David Hubbard Signed-off-by: Paul Menzel Reviewed-on: http://review.coreboot.org/3200 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/asus/f2a85-m/romstage.c | 3 ++- src/southbridge/amd/agesa/hudson/Makefile.inc | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index b7bcf43d5e..5773eba047 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -101,7 +101,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* set DDR3 voltage */ byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; - if (!byte) + /* default is byte = 0x0, so no need to set it in this case */ + if (byte) do_smbus_write_byte(0xb20, 0x15, 0x3, byte); } diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index da029a0383..7802600c4e 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -1,3 +1,4 @@ +romstage-y += smbus.c ramstage-y += hudson.c ramstage-y += usb.c ramstage-y += lpc.c