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amd/agesa: Implicit assigment between enum without cast 

Change-Id: I31632948ce69b2d1ff63b6c920016ed6fdf9e2f8
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5760
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Edward O'Callaghan 2014-05-15 21:23:51 +10:00 committed by Marc Jones
parent e1845b38c7
commit b2d68976c8
3 changed files with 3 additions and 3 deletions
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2
src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c
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@ -206,7 +206,7 @@ MemNSyncTargetSpeedNb (
ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ?
((MEMORY_BUS_SPEED)ChnlTmgMod[1] >= DDR667_FREQUENCY) :
((MEMORY_BUS_SPEED)ChnlTmgMod[1] <= DDR1066_FREQUENCY));
MemClkFreq = ChnlTmgMod[1];
MemClkFreq = (MEMORY_BUS_SPEED) ChnlTmgMod[1];
}
}

2
src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c
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@ -178,7 +178,7 @@ MemNSyncTargetSpeedNb (
// ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ?
// (ChnlTmgMod[1] >= DDR667_FREQUENCY) :
// (ChnlTmgMod[1] <= DDR1066_FREQUENCY));
MemClkFreq = ChnlTmgMod[1];
MemClkFreq = (MEMORY_BUS_SPEED) ChnlTmgMod[1];
}
}

2
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c
View File

@ -186,7 +186,7 @@ MemNSyncTargetSpeedNb (
ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ?
((MEMORY_BUS_SPEED)(ChnlTmgMod[1]) >= DDR667_FREQUENCY) :
((MEMORY_BUS_SPEED)(ChnlTmgMod[1]) <= DDR1066_FREQUENCY));
MemClkFreq = ChnlTmgMod[1];
MemClkFreq = (MEMORY_BUS_SPEED) ChnlTmgMod[1];
}
}