pit: Fix some settings for the exynos5420 CPU.

Some of the settings which were defaulted to or automatically selected for the
exynos5420 which were inherited from the exynos5250 were not correct for this
SOC.

Change-Id: I11ffd8a6b80628405ac493fe2139f79c05d15d7e
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3645
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Gabe Black 2013-05-13 15:56:53 -07:00 committed by Stefan Reinauer
parent 607c0b6d63
commit b2d811aa9e
1 changed files with 8 additions and 14 deletions

View File

@ -17,13 +17,13 @@ config BL1_SIZE_KB
# Example SRAM/iRAM map for Exynos5420 platform:
#
# 0x0202_0000: vendor-provided BL1
# 0x0202_3400: bootblock, assume up to 32KB in size
# 0x0202_4400: bootblock, assume up to 32KB in size
# 0x0203_0000: romstage, assume up to 128KB in size.
# 0x0207_8000: stack pointer
# 0x0207_4000: stack pointer
config BOOTBLOCK_BASE
hex
default 0x02023400
default 0x02024400
config ROMSTAGE_BASE
hex
@ -40,11 +40,11 @@ config ROMSTAGE_SIZE
# consecutive memory locations ending just below SP
config STACK_TOP
hex
default 0x02078000
default 0x02074000
config STACK_BOTTOM
hex
default 0x02077000
default 0x02073000
config STACK_SIZE
hex
@ -69,13 +69,7 @@ config CBFS_CACHE_ADDRESS
config CBFS_CACHE_SIZE
hex "size of CBFS cache data"
default 0x000017000
# FIXME: This is for copying SPI content into SRAM temporarily and
# will be removed when we have the SPI streaming driver implemented.
config SPI_IMAGE_HACK
hex
default 0x02060000
default 0x000013000
# FIXME: other magic numbers that should probably go away
config XIP_ROM_SIZE
@ -84,11 +78,11 @@ config XIP_ROM_SIZE
config SYS_SDRAM_BASE
hex
default 0x40000000
default 0x20000000
config SYS_TEXT_BASE
hex
default 0x43e00000
default 0x23e00000
config COREBOOT_TABLES_SIZE
hex