sb/intel/bd82x6x: Assign unique bus/dev/fn for I/O APIC + HPETs
Assign unique bus/dev/fn values for the I/O APIC and each HPET. The values are taken from an example DMAR table. They are used as source-id for MSI requests and as completer-id for reads from the device' MMIO space [1, 2]. The former is usefull for source-id verfication during interrupt remapping. [1] Intel 6 Series Chipset and Intel C200 Series Chipset Datasheet Document-Number: 324645 [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) Datasheet Document-Number: 326776 Change-Id: Ib46f8cfb7d966dd1cf2b026f671bc45ffcc43d25 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12193 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -51,6 +51,10 @@ static void pch_enable_ioapic(struct device *dev)
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{
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u32 reg32;
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/* Assign unique bus/dev/fn for I/O APIC */
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pci_write_config16(dev, LPC_IBDF,
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PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
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/* Enable ACPI I/O range decode */
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pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
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@ -375,9 +379,15 @@ static void ppt_pm_init(struct device *dev)
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RCBA32_AND_OR(0x21b0, ~0UL, 0xf);
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}
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static void enable_hpet(void)
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static void enable_hpet(struct device *const dev)
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{
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u32 reg32;
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size_t i;
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/* Assign unique bus/dev/fn for each HPET */
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for (i = 0; i < 8; ++i)
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pci_write_config16(dev, LPC_HnBDF(i),
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PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i);
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/* Move HPET to default address 0xfed00000 and enable it */
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reg32 = RCBA32(HPTC);
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@ -531,7 +541,7 @@ static void lpc_init(struct device *dev)
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isa_dma_init();
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/* Initialize the High Precision Event Timers, if present. */
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enable_hpet();
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enable_hpet(dev);
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/* Initialize Clock Gating */
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enable_clock_gating(dev);
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@ -120,6 +120,10 @@ early_usb_init (const struct southbridge_usb_port *portmap);
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#define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0)
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#define PCH_ME_DEV PCI_DEV(0, 0x16, 0)
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#define PCH_PCIE_DEV_SLOT 28
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#define PCH_IOAPIC_PCI_BUS 250
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#define PCH_IOAPIC_PCI_SLOT 31
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#define PCH_HPET_PCI_BUS 250
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#define PCH_HPET_PCI_SLOT 15
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/* PCI Configuration Space (D31:F0): LPC */
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#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0)
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@ -159,6 +163,9 @@ early_usb_init (const struct southbridge_usb_port *portmap);
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#define PIRQG_ROUT 0x6A
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#define PIRQH_ROUT 0x6B
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#define LPC_IBDF 0x6C /* I/O APIC bus/dev/fn */
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#define LPC_HnBDF(n) (0x70 + n * 2) /* HPET n bus/dev/fn */
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#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
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#define LPC_EN 0x82 /* LPC IF Enables Register */
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#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
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