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sb/intel/bd82x6x: Assign unique bus/dev/fn for I/O APIC + HPETs 

Assign unique bus/dev/fn values for the I/O APIC and each HPET. The
values are taken from an example DMAR table. They are used as source-id
for MSI requests and as completer-id for reads from the device' MMIO
space [1, 2]. The former is usefull for source-id verfication during
interrupt remapping.

[1] Intel 6 Series Chipset and Intel C200 Series Chipset
    Datasheet
    Document-Number: 324645

[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH)
    Datasheet
    Document-Number: 326776

Change-Id: Ib46f8cfb7d966dd1cf2b026f671bc45ffcc43d25
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12193
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Nico Huber 2015-10-26 12:34:02 +01:00 committed by Patrick Georgi
parent bc39b488a5
commit b2dae79301
2 changed files with 19 additions and 2 deletions
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14
src/southbridge/intel/bd82x6x/lpc.c
View File

@ -51,6 +51,10 @@ static void pch_enable_ioapic(struct device *dev)
{ {
u32 reg32; u32 reg32;
/* Assign unique bus/dev/fn for I/O APIC */
pci_write_config16(dev, LPC_IBDF,
PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
/* Enable ACPI I/O range decode */ /* Enable ACPI I/O range decode */
pci_write_config8(dev, ACPI_CNTL, ACPI_EN); pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
@ -375,9 +379,15 @@ static void ppt_pm_init(struct device *dev)
RCBA32_AND_OR(0x21b0, ~0UL, 0xf); RCBA32_AND_OR(0x21b0, ~0UL, 0xf);
} }
static void enable_hpet(void) static void enable_hpet(struct device *const dev)
{ {
u32 reg32; u32 reg32;
size_t i;
/* Assign unique bus/dev/fn for each HPET */
for (i = 0; i < 8; ++i)
pci_write_config16(dev, LPC_HnBDF(i),
PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i);
/* Move HPET to default address 0xfed00000 and enable it */ /* Move HPET to default address 0xfed00000 and enable it */
reg32 = RCBA32(HPTC); reg32 = RCBA32(HPTC);
@ -531,7 +541,7 @@ static void lpc_init(struct device *dev)
isa_dma_init(); isa_dma_init();
/* Initialize the High Precision Event Timers, if present. */ /* Initialize the High Precision Event Timers, if present. */
enable_hpet(); enable_hpet(dev);
/* Initialize Clock Gating */ /* Initialize Clock Gating */
enable_clock_gating(dev); enable_clock_gating(dev);

7
src/southbridge/intel/bd82x6x/pch.h
View File

@ -120,6 +120,10 @@ early_usb_init (const struct southbridge_usb_port *portmap);
#define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0) #define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0)
#define PCH_ME_DEV PCI_DEV(0, 0x16, 0) #define PCH_ME_DEV PCI_DEV(0, 0x16, 0)
#define PCH_PCIE_DEV_SLOT 28 #define PCH_PCIE_DEV_SLOT 28
#define PCH_IOAPIC_PCI_BUS 250
#define PCH_IOAPIC_PCI_SLOT 31
#define PCH_HPET_PCI_BUS 250
#define PCH_HPET_PCI_SLOT 15
/* PCI Configuration Space (D31:F0): LPC */ /* PCI Configuration Space (D31:F0): LPC */
#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0)
@ -159,6 +163,9 @@ early_usb_init (const struct southbridge_usb_port *portmap);
#define PIRQG_ROUT 0x6A #define PIRQG_ROUT 0x6A
#define PIRQH_ROUT 0x6B #define PIRQH_ROUT 0x6B
#define LPC_IBDF 0x6C /* I/O APIC bus/dev/fn */
#define LPC_HnBDF(n) (0x70 + n * 2) /* HPET n bus/dev/fn */
#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
#define LPC_EN 0x82 /* LPC IF Enables Register */ #define LPC_EN 0x82 /* LPC IF Enables Register */
#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */