mb/starlabs/starbook: Add Alder Lake StarBook Mk VI variant
Tested using `edk2` from `github.com/starlabsltd/edk2/tree/uefipayload_202209`: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21 No known issues. https://starlabs.systems/pages/starbook-specification Signed-off-by: Ben-StarLabs <ben@starlabs.systems> Change-Id: Idc0c265a88b19cf9e89cc8ab3e8db9abd8cf8409 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65785 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
This commit is contained in:
Ben-StarLabs
Felix Held
parent
1c3da3f236
commit
b2db3659a9
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@ -185,6 +185,7 @@ The boards in this section are not real mainboards, but emulators.
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- [StarLite Mk III](starlabs/lite_glk.md)
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- [StarLite Mk IV](starlabs/lite_glkr.md)
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- [StarBook Mk V](starlabs/starbook_tgl.md)
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- [StarBook Mk VI](starlabs/starbook_adl.md)
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- [Flashing devices](starlabs/common/flashing.md)
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## Supermicro
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@ -0,0 +1,86 @@
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# StarBook Mk V
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## Specs
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- CPU (full processor specs available at https://ark.intel.com)
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- Intel i7-1260P (Alder Lake)
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- Intel i3-1220P (Alder Lake)
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- EC
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- ITE IT5570E
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- Backlit keyboard, with standard PS/2 keycodes and SCI hotkeys
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- Battery
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- Charger, using AC adapter or USB-C PD
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- Suspend / resume
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- GPU
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- Intel® Iris® Xe Graphics
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- GOP driver is recommended, VBT is provided
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- eDP 14-inch 1920x1080 LCD
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- HDMI video
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- USB-C DisplayPort video
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- Memory
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- 2 x DDR4 SODIMM
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- Networking
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- AX210 2230 WiFi / Bluetooth
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- Sound
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- Realtek ALC269-VB6
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- Internal speakers
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- Internal microphone
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- Combined headphone / microphone 3.5-mm jack
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- HDMI audio
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- USB-C DisplayPort audio
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- Storage
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- M.2 PCIe SSD
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- RTS5129 MicroSD card reader
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- USB
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- 1920x1080 CCD camera
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- USB 3.1 Gen 2 (left)
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- USB 3.1 Gen 2 Type-A (left)
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- USB 3.1 Gen 1 Type-A (right)
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- USB 2.0 Type-A (right)
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## Building coreboot
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### Preliminaries
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Prior to building coreboot the following files are required:
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* Intel Flash Descriptor file (descriptor.bin)
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* Intel Management Engine firmware (me.bin)
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* ITE Embedded Controller firmware (ec.bin)
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The files listed below are optional:
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- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
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These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
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### Build
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The following commands will build a working image:
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```bash
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make distclean
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make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_adl
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make
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```
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## Flashing coreboot
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```eval_rst
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+---------------------+------------+
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| Type | Value |
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+=====================+============+
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| Socketed flash | no |
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+---------------------+------------+
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| Vendor | Winbond |
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+---------------------+------------+
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| Model | W25Q256.V |
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+---------------------+------------+
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| Size | 32 MiB |
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+---------------------+------------+
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| Package | SOIC-8 |
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+---------------------+------------+
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| Internal flashing | yes |
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+---------------------+------------+
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| External flashing | yes |
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+---------------------+------------+
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Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.
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@ -55,11 +55,29 @@ config BOARD_STARLABS_STARBOOK_TGL
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select SPI_FLASH_WINBOND
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select TPM_MEASURED_BOOT
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config BOARD_STARLABS_STARBOOK_ADL
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select BOARD_ROMSIZE_KB_32768
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select BOARD_STARLABS_STARBOOK_SERIES
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select DRIVERS_INTEL_PMC
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select EC_STARLABS_KBL_LEVELS
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select EC_STARLABS_MAX_CHARGE
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select EC_STARLABS_MIRROR_FLAG
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select EC_STARLABS_NEED_ITE_BIN
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select MEMORY_MAPPED_TPM
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select MAINBOARD_HAS_TPM2
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select SOC_INTEL_ALDERLAKE
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select SOC_INTEL_ALDERLAKE_PCH_P
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select SOC_INTEL_ALDERLAKE_S3
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select SPI_FLASH_WINBOND
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select TPM_MEASURED_BOOT
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select PCIEXP_SUPPORT_RESIZABLE_BARS
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if BOARD_STARLABS_STARBOOK_SERIES
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config CCD_PORT
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int
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default 6 if BOARD_STARLABS_LABTOP_CML
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default 4 if BOARD_STARLABS_STARBOOK_ADL
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default 3
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config CMOS_DEFAULT_FILE
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@ -72,13 +90,13 @@ config DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
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config DIMM_SPD_SIZE
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default 512 if BOARD_STARLABS_LABTOP_KBL
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default 512
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config DRIVER_TPM_SPI_CHIP
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default 2
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config EC_GPE_SCI
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default 0x6e if BOARD_STARLABS_STARBOOK_TGL
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default 0x6e if BOARD_STARLABS_STARBOOK_TGL || BOARD_STARLABS_STARBOOK_ADL
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default 0x50
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config EC_STARLABS_ADD_ITE_BIN
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@ -93,6 +111,7 @@ config EC_VARIANT_DIR
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default "kbl" if !EC_STARLABS_MERLIN && BOARD_STARLABS_LABTOP_KBL
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default "cml" if !EC_STARLABS_MERLIN && BOARD_STARLABS_LABTOP_CML
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default "tgl" if !EC_STARLABS_MERLIN && BOARD_STARLABS_STARBOOK_TGL
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default "adl" if !EC_STARLABS_MERLIN && BOARD_STARLABS_STARBOOK_ADL
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config FMDFILE
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
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@ -109,14 +128,16 @@ config MAINBOARD_FAMILY
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default "L3" if BOARD_STARLABS_LABTOP_KBL
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default "L4" if BOARD_STARLABS_LABTOP_CML
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default "B5" if BOARD_STARLABS_STARBOOK_TGL
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default "B6-I" if BOARD_STARLABS_STARBOOK_ADL
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config MAINBOARD_PART_NUMBER
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default "LabTop Mk III" if BOARD_STARLABS_LABTOP_KBL
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default "LabTop Mk IV" if BOARD_STARLABS_LABTOP_CML
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default "StarBook Mk V" if BOARD_STARLABS_STARBOOK_TGL
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default "StarBook Mk VI" if BOARD_STARLABS_STARBOOK_ADL
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config MAINBOARD_SMBIOS_PRODUCT_NAME
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default "StarBook" if BOARD_STARLABS_STARBOOK_TGL
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default "StarBook" if BOARD_STARLABS_STARBOOK_TGL || BOARD_STARLABS_STARBOOK_ADL
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default "LabTop"
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config ME_BIN_PATH
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@ -127,15 +148,23 @@ config EDK2_BOOTSPLASH_FILE
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string
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default "3rdparty/blobs/mainboard/starlabs/Logo.bmp"
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config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS
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default 32
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config SOC_INTEL_CSE_SEND_EOP_EARLY
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default n if BOARD_STARLABS_STARBOOK_ADL
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config UART_FOR_CONSOLE
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default 0 if BOARD_STARLABS_STARBOOK_ADL
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default 2
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config USE_PM_ACPI_TIMER
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default n if BOARD_STARLABS_STARBOOK_TGL
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default n if BOARD_STARLABS_STARBOOK_TGL || BOARD_STARLABS_STARBOOK_ADL
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config VARIANT_DIR
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default "kbl" if BOARD_STARLABS_LABTOP_KBL
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default "cml" if BOARD_STARLABS_LABTOP_CML
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default "tgl" if BOARD_STARLABS_STARBOOK_TGL
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default "adl" if BOARD_STARLABS_STARBOOK_ADL
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endif
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@ -8,3 +8,6 @@ config BOARD_STARLABS_LABTOP_CML
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config BOARD_STARLABS_STARBOOK_TGL
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bool "Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)"
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config BOARD_STARLABS_STARBOOK_ADL
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bool "Star Labs StarBook Mk VI (i3-1220P and i7-1260P)"
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@ -7,7 +7,7 @@ DefinitionBlock(
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725
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0x20220930
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)
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{
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#include <acpi/dsdt_top.asl>
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@ -30,6 +30,9 @@ DefinitionBlock(
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/tigerlake/acpi/southbridge.asl>
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#include <soc/intel/tigerlake/acpi/tcss.asl>
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#elif CONFIG(SOC_INTEL_ALDERLAKE)
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/alderlake/acpi/southbridge.asl>
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#endif
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/* PS/2 Keyboard */
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@ -0,0 +1,9 @@
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += gpio.c
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romstage-y += romstage.c
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ramstage-y += devtree.c
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ramstage-y += gpio.c
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ramstage-y += hda_verb.c
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@ -0,0 +1,14 @@
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FLASH 0x2000000 {
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SI_ALL 0x1000000 {
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SI_DESC 0x1000
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SI_ME
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}
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SI_BIOS 0x1000000 {
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EC@0x0 0x20000
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RW_MRC_CACHE@0x20000 0x10000
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SMMSTORE@0x30000 0x40000
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CONSOLE@0x70000 0x20000
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FMAP@0x90000 0x1000
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COREBOOT(CBFS)
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}
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}
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Binary file not shown.
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@ -0,0 +1,176 @@
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chip soc/intel/alderlake
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# Graphics
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# TODO:
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# register "panel_cfg" = "{
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# .up_delay_ms = 200, // T3
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# .backlight_on_delay_ms = 0, // T7
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# .backlight_off_delay_ms = 50, // T9
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# .down_delay_ms = 0, // T10
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# .cycle_delay_ms = 500, // T12
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# .backlight_pwm_hz = 200, // PWM
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# }"
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# FSP Memory
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register "enable_c6dram" = "1"
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register "sagv" = "SaGv_Enabled"
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# FSP Silicon
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register "eist_enable" = "1"
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# Serial I/O
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register "serial_io_i2c_mode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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}"
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register "serial_io_uart_mode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
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}"
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# Power
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register "pch_slp_s3_min_assertion_width" = "2" # 50ms
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register "pch_slp_s4_min_assertion_width" = "3" # 1s
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register "pch_slp_sus_min_assertion_width" = "3" # 500ms
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register "pch_slp_a_min_assertion_width" = "3" # 2s
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# PM Util
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register "pmc_gpe0_dw0" = "GPP_B"
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register "pmc_gpe0_dw1" = "GPP_C"
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register "pmc_gpe0_dw2" = "GPP_E"
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# Device Tree
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device ref igpu on
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register "ddi_portA_config" = "1"
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register "ddi_ports_config" = "{
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[DDI_PORT_A] = DDI_ENABLE_HPD,
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[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
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}"
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end
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device ref gna on end
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device ref crashlog off end
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device ref xhci on
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# Motherboard USB Type C
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC3)"
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"
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# Motherboard USB 3.0
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register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
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# Daughterboard USB 3.0
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"
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# Internal Webcam
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register "usb2_ports[CONFIG_CCD_PORT]" = "USB2_PORT_MID(OC_SKIP)"
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# Fingerprint Reader
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"
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# Daughterboard SD Card
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register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"
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# Internal Bluetooth
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"
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end
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device ref i2c0 on
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chip drivers/i2c/hid
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register "generic.hid" = ""STAR0001""
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register "generic.desc" = ""Touchpad""
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register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E12_IRQ)"
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register "hid_desc_reg_offset" = "0x20"
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device i2c 2c on end
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end
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end
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device ref shared_sram on end
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device ref heci1 on end
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device ref sata on
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register "sata_salp_support" = "1"
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register "sata_ports_enable[1]" = "1"
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register "sata_ports_dev_slp[1]" = "1"
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end
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device ref pcie_rp5 on # WiFi
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
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end
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register "pch_pcie_rp[PCH_RP(5)]" = "{
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.clk_src = 2,
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.clk_req = 2,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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smbios_slot_desc "SlotTypePciExpressGen3X1"
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"SlotLengthShort"
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"M.2/M 2230"
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"SlotDataBusWidth1X"
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)"
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register "srcclk_pin" = "2"
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device generic 0 on end
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end
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end
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device ref pcie_rp9 on # SSD x4
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register "pch_pcie_rp[PCH_RP(9)]" = "{
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.clk_src = 1,
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.clk_req = 1,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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smbios_slot_desc "SlotTypeM2Socket3"
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"SlotLengthLong"
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"M.2/M 2280"
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"SlotDataBusWidth4X"
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)"
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register "srcclk_pin" = "1"
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device generic 0 on end
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end
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end
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device ref uart0 on end
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device ref pch_espi on
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register "gen1_dec" = "0x00fc0201"
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register "gen2_dec" = "0x00000381"
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register "gen3_dec" = "0x00000511"
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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chip ec/starlabs/merlin
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# Port pair 4Eh/4Fh
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device pnp 4e.00 on end # IO Interface
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device pnp 4e.01 off end # Com 1
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device pnp 4e.02 off end # Com 2
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device pnp 4e.04 off end # System Wake-Up
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device pnp 4e.05 off end # PS/2 Mouse
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device pnp 4e.06 on # PS/2 Keyboard
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io 0x60 = 0x0060
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io 0x62 = 0x0064
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irq 0x70 = 1
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end
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device pnp 4e.0a off end # Consumer IR
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device pnp 4e.0f off end # Shared Memory/Flash Interface
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device pnp 4e.10 off end # RTC-like Timer
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device pnp 4e.11 off end # Power Management Channel 1
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device pnp 4e.12 off end # Power Management Channel 2
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device pnp 4e.13 off end # Serial Peripheral Interface
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device pnp 4e.14 off end # Platform EC Interface
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device pnp 4e.17 off end # Power Management Channel 3
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device pnp 4e.18 off end # Power Management Channel 4
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device pnp 4e.19 off end # Power Management Channel 5
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end
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end
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device ref p2sb on end
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device ref hda on
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register "pch_hda_idisp_codec_enable" = "1"
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register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
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register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
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end
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device ref smbus on end
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end
|
||||
end
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <chip.h>
|
||||
#include <cpu/intel/turbo.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <option.h>
|
||||
#include <types.h>
|
||||
#include <variants.h>
|
||||
|
||||
void devtree_update(void)
|
||||
{
|
||||
config_t *cfg = config_of_soc();
|
||||
|
||||
struct soc_power_limits_config *soc_conf_10core =
|
||||
&cfg->power_limits_config[ADL_P_282_482_28W_CORE];
|
||||
|
||||
struct soc_power_limits_config *soc_conf_12core =
|
||||
&cfg->power_limits_config[ADL_P_682_28W_CORE];
|
||||
|
||||
struct device *nic_dev = pcidev_on_root(0x1c, 4);
|
||||
|
||||
/* Update PL1 & PL2 based on CMOS settings */
|
||||
switch (get_power_profile(PP_POWER_SAVER)) {
|
||||
case PP_POWER_SAVER:
|
||||
disable_turbo();
|
||||
soc_conf_10core->tdp_pl1_override = 15;
|
||||
soc_conf_12core->tdp_pl1_override = 15;
|
||||
soc_conf_10core->tdp_pl2_override = 15;
|
||||
soc_conf_12core->tdp_pl2_override = 15;
|
||||
// TODO:common_config->pch_thermal_trip = 20;
|
||||
break;
|
||||
case PP_BALANCED:
|
||||
soc_conf_10core->tdp_pl1_override = 15;
|
||||
soc_conf_12core->tdp_pl1_override = 15;
|
||||
soc_conf_10core->tdp_pl2_override = 25;
|
||||
soc_conf_12core->tdp_pl2_override = 25;
|
||||
// TODO:common_config->pch_thermal_trip = 15;
|
||||
break;
|
||||
case PP_PERFORMANCE:
|
||||
soc_conf_10core->tdp_pl1_override = 28;
|
||||
soc_conf_12core->tdp_pl1_override = 28;
|
||||
soc_conf_10core->tdp_pl2_override = 40;
|
||||
soc_conf_12core->tdp_pl2_override = 40;
|
||||
// TODO:common_config->pch_thermal_trip = 10;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Enable/Disable Wireless based on CMOS settings */
|
||||
if (get_uint_option("wireless", 1) == 0)
|
||||
nic_dev->enabled = 0;
|
||||
|
||||
/* Enable/Disable Webcam based on CMOS settings */
|
||||
if (get_uint_option("webcam", 1) == 0)
|
||||
cfg->usb2_ports[CONFIG_CCD_PORT].enable = 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,459 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <variants.h>
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
const struct pad_config early_gpio_table[] = {
|
||||
/* H10: UART0 RXD Debug Connector */
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
|
||||
/* H11: UART0 TXD Debug Connector */
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
|
||||
};
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
const struct pad_config gpio_table[] = {
|
||||
/* GPD0: Battery Low */
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
/* GPD1: Charger Connected */
|
||||
PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
|
||||
/* GPD2: LAN Wake */
|
||||
PAD_NC(GPD2, NONE),
|
||||
/* GPD3: Power Button */
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
|
||||
/* GPD4: Sleep S3 */
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
/* GPD5: Sleep S4 */
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
/* GPD6: Sleep A */
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
/* GPD7: Power Adapter Disable */
|
||||
PAD_CFG_GPO(GPD7, 0, PWROK),
|
||||
/* GPD8: Suspend Clock */
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
/* GPD9: Wireless LAN Sleep */
|
||||
PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
|
||||
/* GPD10: Sleep S5 */
|
||||
PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
/* GPD11: LAN PHY Enable */
|
||||
PAD_NC(GPD11, NONE),
|
||||
|
||||
/* A0: ESPI IO 0 */
|
||||
/* A1: ESPI IO 1 */
|
||||
/* A2: ESPI IO 2 */
|
||||
/* A3: ESPI IO 3 */
|
||||
/* A4: ESPI CS 0 */
|
||||
/* A5: Not Connected */
|
||||
PAD_NC(GPP_A5, NONE),
|
||||
/* A6: Not Connected */
|
||||
PAD_NC(GPP_A6, NONE),
|
||||
/* A7: Embedded Controller SCI */
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_A7, NONE, PLTRST, LEVEL),
|
||||
/* A8: Not Connected */
|
||||
PAD_NC(GPP_A8, NONE),
|
||||
/* A9: ESPI Clock */
|
||||
/* A10: ESPI Reset */
|
||||
/* A11: Not Connected */
|
||||
PAD_NC(GPP_A11, NONE),
|
||||
/* A12: PCH M.2 SSD PEDET */
|
||||
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
|
||||
/* A13: BlueTooth RF Kill */
|
||||
PAD_CFG_GPO(GPP_A13, 1, DEEP),
|
||||
/* A14: Test Point 45 */
|
||||
PAD_NC(GPP_A14, NONE),
|
||||
/* A15: Test Point 52 */
|
||||
PAD_NC(GPP_A15, NONE),
|
||||
/* A16: USB OverCurrent 3 */
|
||||
PAD_NC(GPP_A16, NONE),
|
||||
/* A17: Not Connected */
|
||||
PAD_NC(GPP_A17, NONE),
|
||||
/* A18: DDI B DP HPD */
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
/* A19: TCP0 HPD */
|
||||
PAD_NC(GPP_A19, NONE),
|
||||
/* A20: Test Point 44 */
|
||||
PAD_NC(GPP_A20, NONE),
|
||||
/* A21: Fingerprint Reader Interrupt */
|
||||
PAD_NC(GPP_A21, NONE),
|
||||
/* A22: Fingerprint Reader Reset */
|
||||
PAD_NC(GPP_A22, NONE),
|
||||
/* A23: Not Connected */
|
||||
PAD_NC(GPP_A23, NONE),
|
||||
|
||||
|
||||
/* B0: Core Vendor ID 0 */
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
/* B1: Core Vendor ID 1 */
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
/* B2: BC PROCHOT */
|
||||
PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),
|
||||
/* B3: Not Connected */
|
||||
PAD_NC(GPP_B3, NONE),
|
||||
/* B4: Not Connected */
|
||||
PAD_NC(GPP_B4, NONE),
|
||||
/* B5: I2C 2 SDA Touch Panel SDA */
|
||||
PAD_NC(GPP_B5, NONE),
|
||||
/* B6: I2C 2 SCL Touch Panel Clock */
|
||||
PAD_NC(GPP_B6, NONE),
|
||||
/* B7: I2C 3 SDA Test Point 15 */
|
||||
PAD_NC(GPP_B7, NONE),
|
||||
/* B8: I2C 3 SCL Test Point 16 */
|
||||
PAD_NC(GPP_B8, NONE),
|
||||
/* B9: Not Connected */
|
||||
PAD_NC(GPP_B9, NONE),
|
||||
/* B10: Not Connected */
|
||||
PAD_NC(GPP_B10, NONE),
|
||||
/* B11: I2C PMC PD Interrupt Test Point 28 */
|
||||
PAD_NC(GPP_B11, NONE),
|
||||
/* B12: PM SLP S0 */
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
/* B13: PLT RST */
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
/* B14: Top Swap Override Weak Internal PD 20K
|
||||
High: Enabled
|
||||
Low: Disabled */
|
||||
PAD_CFG_GPO(GPP_B14, 0, PLTRST),
|
||||
/* B15: Not Connected */
|
||||
PAD_NC(GPP_B15, NONE),
|
||||
/* B16: Not Connected */
|
||||
PAD_NC(GPP_B16, NONE),
|
||||
/* B17: Not Connected */
|
||||
PAD_NC(GPP_B17, NONE),
|
||||
/* B18: Reboot Support Weak Internal PD 20K
|
||||
High: Disabled
|
||||
Low: Enabled */
|
||||
PAD_NC(GPP_B18, NONE),
|
||||
/* B19: Not Connected */
|
||||
PAD_NC(GPP_B19, NONE),
|
||||
/* B20: Not Connected */
|
||||
PAD_NC(GPP_B20, NONE),
|
||||
/* B21: Not Connected */
|
||||
PAD_NC(GPP_B21, NONE),
|
||||
/* B22: Not Connected */
|
||||
PAD_NC(GPP_B22, NONE),
|
||||
/* B23: Not used MiPi Camera */
|
||||
PAD_NC(GPP_B23, NONE),
|
||||
/* B24: Not Connected */
|
||||
PAD_NC(GPP_B24, NONE),
|
||||
/* B25: Not Connected */
|
||||
PAD_NC(GPP_B25, NONE),
|
||||
|
||||
/* C0: SMB Clock */
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
/* C1: SMB Data */
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
/* C2: TLS Confidentiality Weak Internal PD 20K
|
||||
Low: Disabled
|
||||
High: Enabled */
|
||||
PAD_CFG_GPO(GPP_C2, 1, PLTRST),
|
||||
/* C3: SML 0 Clock */
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
/* C4: SML 0 Data */
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
/* C5: Boot Strap Weak Internal PD 20K
|
||||
Low: ESPI
|
||||
High: Disabled */
|
||||
PAD_CFG_GPO(GPP_C5, 0, DEEP),
|
||||
/* C6: SML 1 Clock */
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
|
||||
/* C7: SML 1 Data */
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
|
||||
/* C8: Not Connected */
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
/* C9: Not Connected */
|
||||
PAD_NC(GPP_C9, NONE),
|
||||
/* C10: Not Connected */
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
/* C11: Not Connected */
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
/* C12: Not Connected */
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
/* C13: Not Connected */
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
/* C14: Not Connected */
|
||||
PAD_NC(GPP_C14, NONE),
|
||||
/* C15: Not Connected */
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
/* C16: Not Connected */
|
||||
PAD_NC(GPP_C16, NONE),
|
||||
/* C17: Not Connected */
|
||||
PAD_NC(GPP_C17, NONE),
|
||||
/* C18: Not Connected */
|
||||
PAD_NC(GPP_C18, NONE),
|
||||
/* C19: Not Connected */
|
||||
PAD_NC(GPP_C19, NONE),
|
||||
/* C20: Not Connected */
|
||||
PAD_NC(GPP_C20, NONE),
|
||||
/* C21: Not Connected */
|
||||
PAD_NC(GPP_C21, NONE),
|
||||
/* C22: Not Connected */
|
||||
PAD_NC(GPP_C22, NONE),
|
||||
/* C23: Not Connected */
|
||||
PAD_NC(GPP_C23, NONE),
|
||||
|
||||
/* D0: Not used Audio ID 0 */
|
||||
PAD_NC(GPP_D0, NONE),
|
||||
/* D1: Not used Audio ID 1 */
|
||||
PAD_NC(GPP_D1, NONE),
|
||||
/* D2: Not used Audio ID 2 */
|
||||
PAD_NC(GPP_D2, NONE),
|
||||
/* D3: Not Connected */
|
||||
PAD_NC(GPP_D3, NONE),
|
||||
/* D4: Not Connected */
|
||||
PAD_NC(GPP_D4, NONE),
|
||||
/* D5: Not Connected */
|
||||
PAD_NC(GPP_D5, NONE),
|
||||
/* D6: Clock Request 1 PCH M.2 SSD */
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
|
||||
/* D7: Clock Request 2 Wireless LAN */
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
/* D8: Clock Request 3 LAN */
|
||||
PAD_NC(GPP_D8, NONE),
|
||||
/* D9: GSPI 2 FPS */
|
||||
PAD_NC(GPP_D9, NONE),
|
||||
/* D10: GSPI 2 Clock */
|
||||
PAD_NC(GPP_D10, NONE),
|
||||
/* D11: GSPI 2 MISO FPS */
|
||||
PAD_NC(GPP_D11, NONE),
|
||||
/* D12: GSPI 2 MOSI FPS */
|
||||
PAD_NC(GPP_D12, NONE),
|
||||
/* D13: Wireless LAN Wake */
|
||||
PAD_CFG_GPO(GPP_D13, 1, PLTRST),
|
||||
/* D14: CPU M.2 SSD Power Enable */
|
||||
PAD_NC(GPP_D14, NONE),
|
||||
/* D15: Not Connected */
|
||||
PAD_NC(GPP_D15, NONE),
|
||||
/* D16: PCH M.2 SSD Power Enable */
|
||||
PAD_CFG_GPO(GPP_D16, 1, PLTRST),
|
||||
/* D17: Not used Fingerprint ID */
|
||||
PAD_NC(GPP_D17, NONE),
|
||||
/* D18: Not Connected */
|
||||
PAD_NC(GPP_D18, NONE),
|
||||
/* D19: Test Point 21 */
|
||||
PAD_NC(GPP_D19, NONE),
|
||||
|
||||
/* E0: SATA x PCIe */
|
||||
PAD_NC(GPP_E0, NONE),
|
||||
/* E1: Not used Accelerometer Interrupt */
|
||||
PAD_NC(GPP_E1, NONE),
|
||||
/* E2: Not Connected */
|
||||
PAD_CFG_GPO(GPP_E2, 1, PLTRST),
|
||||
/* E3: WiFi RF Kill */
|
||||
PAD_CFG_GPO(GPP_E3, 1, DEEP),
|
||||
/* E4: Test Point 14 */
|
||||
PAD_NC(GPP_E4, NONE),
|
||||
/* E5: Not Connected */
|
||||
PAD_NC(GPP_E5, NONE),
|
||||
/* E6: JTAG ODT No internal PD
|
||||
Low: Disabled
|
||||
High: Enabled */
|
||||
PAD_CFG_GPO(GPP_E6, 0, DEEP),
|
||||
/* E7: Embedded Controller SMI */
|
||||
PAD_CFG_GPI_SMI_LOW(GPP_E7, NONE, DEEP, EDGE_SINGLE),
|
||||
/* E8: DRAM Sleep */
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
/* E9: USB OverCurrent 0 */
|
||||
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
/* E10: PWD Amplifier Input */
|
||||
PAD_CFG_GPO(GPP_E10, 0, PLTRST),
|
||||
/* E11: TPM IRQ */
|
||||
PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
|
||||
/* E12: Touchpad Interrupt */
|
||||
PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST),
|
||||
/* E13: Not connected */
|
||||
PAD_NC(GPP_E13, NONE),
|
||||
/* E14: EDP HPD */
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
/* E15: Not Connected */
|
||||
PAD_NC(GPP_E15, NONE),
|
||||
/* E16: Not Connected */
|
||||
PAD_NC(GPP_E16, NONE),
|
||||
/* E17: Not Connected */
|
||||
PAD_CFG_GPO(GPP_E17, 1, PLTRST),
|
||||
/* E18: Not Connected */
|
||||
PAD_NC(GPP_E18, NONE),
|
||||
/* E19: Thunderbolt LSX RXD */
|
||||
PAD_NC(GPP_E19, NONE),
|
||||
/* E20: Not Connected */
|
||||
PAD_NC(GPP_E20, NONE),
|
||||
/* E21: Not Connected */
|
||||
PAD_NC(GPP_E21, NONE),
|
||||
/* E22: Not Connected */
|
||||
PAD_NC(GPP_E22, NONE),
|
||||
/* E23: Not Connected */
|
||||
PAD_NC(GPP_E23, NONE),
|
||||
|
||||
/* F0: CNV BRI Data */
|
||||
PAD_NC(GPP_F0, NONE),
|
||||
/* F1: CNV BRI Response */
|
||||
PAD_NC(GPP_F1, NONE),
|
||||
/* F2: CNV RGI Data */
|
||||
PAD_NC(GPP_F2, NONE),
|
||||
/* F3: CNV RGI Response */
|
||||
PAD_NC(GPP_F3, NONE),
|
||||
/* F4: CNV RF Reset */
|
||||
PAD_NC(GPP_F4, NONE),
|
||||
/* F5: Not used MODEM_CLKREQ */
|
||||
PAD_NC(GPP_F5, NONE),
|
||||
/* F6: CNV PA Blanking */
|
||||
PAD_NC(GPP_F6, NONE),
|
||||
/* F7: TBT LSX VCCIO Weak Internal PD 20K
|
||||
Low: 1.8V
|
||||
High: 3.3V */
|
||||
PAD_NC(GPP_F7, NONE),
|
||||
/* F8: Not Connected */
|
||||
PAD_NC(GPP_F8, NONE),
|
||||
/* F9: EC Sleep S0 */
|
||||
PAD_CFG_GPO(GPP_F9, 1, PLTRST),
|
||||
/* F10: Weak Internal PD 20K */
|
||||
PAD_CFG_GPO(GPP_F10, 1, PLTRST),
|
||||
/* F11: TPM ID */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, DEEP, OFF, ACPI),
|
||||
/* F12: Not Connected */
|
||||
PAD_NC(GPP_F12, NONE),
|
||||
/* F13: Not Connected */
|
||||
PAD_NC(GPP_F13, NONE),
|
||||
/* F14: Not Connected */
|
||||
PAD_NC(GPP_F14, NONE),
|
||||
/* F15: Not used Accelerometer Interrupt 2*/
|
||||
PAD_NC(GPP_F15, NONE),
|
||||
/* F16: Not Connected */
|
||||
PAD_CFG_GPO(GPP_F16, 1, RSMRST),
|
||||
/* F17: Not used Touch Panel Reset */
|
||||
PAD_NC(GPP_F17, NONE),
|
||||
/* F18: Not used Touch Panel Interrupt */
|
||||
PAD_NC(GPP_F18, NONE),
|
||||
/* F19: Not Connected */
|
||||
PAD_NC(GPP_F19, NONE),
|
||||
/* F20: CPU M.2 SSD Reset */
|
||||
PAD_NC(GPP_F20, NONE),
|
||||
/* F21: GPPC_F21 */
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
/* F22: Not Connected */
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
/* F23: Not Connected */
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
|
||||
/* H0: PCH M.2 SSD Reset */
|
||||
PAD_CFG_GPO(GPP_H0, 1, PLTRST),
|
||||
/* H1: BFX Strap 2 Bit 3 Weak Internal PD 20K */
|
||||
PAD_CFG_GPO(GPP_H1, 1, PLTRST),
|
||||
/* H2: Wireless LAN Reset */
|
||||
PAD_CFG_GPO(GPP_H2, 1, PLTRST),
|
||||
/* H3: Not Connected */
|
||||
PAD_NC(GPP_H3, NONE),
|
||||
/* H4: I2C 0 SDA Touchpad */
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
/* H5: I2C 0 SDL Touchpad */
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
/* H6: Not Connected */
|
||||
PAD_NC(GPP_H6, NONE),
|
||||
/* H7: Not Connected */
|
||||
PAD_NC(GPP_H7, NONE),
|
||||
/* H8: I2C 4 SDA GSensor */
|
||||
PAD_NC(GPP_H8, NONE),
|
||||
/* H9: I2C 4 SDL GSensor */
|
||||
PAD_NC(GPP_H9, NONE),
|
||||
/* H12: Not Connected */
|
||||
PAD_NC(GPP_H12, NONE),
|
||||
/* H13: PCH M.2 SSD Device Sleep */
|
||||
PAD_CFG_GPO(GPP_H13, 0, PLTRST),
|
||||
/* H14: Not Connected */
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
/* H15: DDPB Control Clock */
|
||||
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
|
||||
/* H16: Not Connected */
|
||||
PAD_NC(GPP_H16, NONE),
|
||||
/* H17: DDPB Control Data */
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
/* H18: CPI C10 Gate */
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
/* H19: Clock Request 4 CPU M.2 SSD */
|
||||
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
|
||||
/* H20: Not Connected */
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
/* H21: Not Connected */
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
/* H22: Not Connected */
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
/* H23: Not Connected */
|
||||
PAD_NC(GPP_H23, NONE),
|
||||
|
||||
/* S0: Not Connected */
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
/* S1: Not Connected */
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
/* S2: DMIC Clock */
|
||||
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
|
||||
/* S3: DMIC Data */
|
||||
PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
|
||||
/* S4: Not Connected */
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
/* S5: Not Connected */
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
/* S6: Not Connected */
|
||||
PAD_NC(GPP_S6, NONE),
|
||||
/* S7: Not Connected */
|
||||
PAD_NC(GPP_S7, NONE),
|
||||
|
||||
/* T0: Not Connected */
|
||||
PAD_NC(GPP_T0, NONE),
|
||||
/* T1: Not Connected */
|
||||
PAD_NC(GPP_T1, NONE),
|
||||
/* T2: Not Connected */
|
||||
PAD_NC(GPP_T2, NONE),
|
||||
/* T3: Not Connected */
|
||||
PAD_NC(GPP_T3, NONE),
|
||||
/* T4: Not Connected */
|
||||
PAD_NC(GPP_T4, NONE),
|
||||
/* T5: Not Connected */
|
||||
PAD_NC(GPP_T5, NONE),
|
||||
/* T6: Not Connected */
|
||||
PAD_NC(GPP_T6, NONE),
|
||||
/* T7: Not Connected */
|
||||
PAD_NC(GPP_T7, NONE),
|
||||
/* T8: Not Connected */
|
||||
PAD_NC(GPP_T8, NONE),
|
||||
/* T9: Not Connected */
|
||||
PAD_NC(GPP_T9, NONE),
|
||||
/* T10: Not Connected */
|
||||
PAD_NC(GPP_T10, NONE),
|
||||
/* T11: Not Connected */
|
||||
PAD_NC(GPP_T11, NONE),
|
||||
/* T12: Not Connected */
|
||||
PAD_NC(GPP_T12, NONE),
|
||||
/* T13: Not Connected */
|
||||
PAD_NC(GPP_T13, NONE),
|
||||
/* T14: Not Connected */
|
||||
PAD_NC(GPP_T14, NONE),
|
||||
/* T15: Not Connected */
|
||||
PAD_NC(GPP_T15, NONE),
|
||||
|
||||
/* R0: HDA BCLK */
|
||||
PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),
|
||||
/* R1: HDA SYNC */
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
/* R2: HDA SDO */
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
/* R3: HDA SDI */
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
/* R4: HDA Reset */
|
||||
PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),
|
||||
/* R5: MiPi Cam Reset */
|
||||
PAD_NC(GPP_R5, NONE),
|
||||
/* R6: Not Connected */
|
||||
PAD_NC(GPP_R6, NONE),
|
||||
/* R7: Not Connected */
|
||||
PAD_NC(GPP_R7, NONE),
|
||||
};
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
#include <stdint.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* coreboot specific header */
|
||||
0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */
|
||||
0x1e507007, /* Subsystem ID */
|
||||
36, /* Number of jacks (NID entries) */
|
||||
|
||||
/* Reset Codec First */
|
||||
AZALIA_RESET(0x1),
|
||||
|
||||
/* HDA Codec Subsystem ID Verb-table */
|
||||
AZALIA_SUBVENDOR(0, 0x1e507007),
|
||||
|
||||
/* Pin Widget Verb-table */
|
||||
AZALIA_PIN_CFG(0, 0x01, 0x00000000),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a61120),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90171110),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x042B1010),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x04AB1020),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x411111F0),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x042b1010),
|
||||
|
||||
/* ALC269 Default 1 */
|
||||
0x02050011,
|
||||
0x02041410,
|
||||
0x02050012,
|
||||
0x02042901,
|
||||
|
||||
/* ALC269 Default 2 */
|
||||
0x0205000d,
|
||||
0x02044440,
|
||||
0x02050007,
|
||||
0x02040040,
|
||||
|
||||
/* ALC269 Default 3 */
|
||||
0x02050002,
|
||||
0x0204aab8,
|
||||
0x02050008,
|
||||
0x02040300,
|
||||
|
||||
/* ALC269 Default 4 */
|
||||
0x02050017,
|
||||
0x020400af,
|
||||
0x02050005,
|
||||
0x020400c0,
|
||||
|
||||
0x80862815, /* Codec Vendor / Device ID: Intel */
|
||||
0x80860101, /* Subsystem ID */
|
||||
9, /* Number of 4 dword sets */
|
||||
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
|
||||
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x08, 0x18561010),
|
||||
AZALIA_PIN_CFG(2, 0x0a, 0x18561010),
|
||||
AZALIA_PIN_CFG(2, 0x0b, 0x18561010),
|
||||
AZALIA_PIN_CFG(2, 0x0c, 0x18561010),
|
||||
AZALIA_PIN_CFG(2, 0x0d, 0x18561010),
|
||||
AZALIA_PIN_CFG(2, 0x0e, 0x18561010),
|
||||
AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <option.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <types.h>
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
const struct mb_cfg mem_config = {
|
||||
.type = MEM_TYPE_DDR4,
|
||||
};
|
||||
|
||||
const bool half_populated = false;
|
||||
|
||||
const struct mem_spd ddr4_spd_info = {
|
||||
.topo = MEM_TOPO_DIMM_MODULE,
|
||||
.smbus = {
|
||||
[0] = {
|
||||
.addr_dimm[0] = 0x50,
|
||||
},
|
||||
[1] = {
|
||||
.addr_dimm[0] = 0x52,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
memcfg_init(mupd, &mem_config, &ddr4_spd_info, half_populated);
|
||||
|
||||
const uint8_t vtd = get_uint_option("vtd", 1);
|
||||
mupd->FspmConfig.VtdDisable = !vtd;
|
||||
};
|
||||
Loading…
Reference in New Issue