vendorcode/intel/fsp: Remove TODOs and make use of EDK2 header
This patch ensures MemInfoHob.h file can make use of existing UEFI headers as is rather than redefining the same structure locally. TEST=Download BIOS_Version_122.3 from external github and build MemInfoHob.h without any compilation error. Change-Id: Ic1e0ad94d8e40ac2aefe9fbcea7d684a97c864b4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -5,7 +5,7 @@
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@copyright
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@copyright
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INTEL CONFIDENTIAL
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INTEL CONFIDENTIAL
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Copyright 1999 - 2017 Intel Corporation.
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Copyright 1999 - 2018 Intel Corporation.
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The source code contained or described herein and all documents related to the
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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source code ("Material") are owned by Intel Corporation or its suppliers or
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@ -37,6 +37,10 @@
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#ifndef _MEM_INFO_HOB_H_
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#ifndef _MEM_INFO_HOB_H_
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#define _MEM_INFO_HOB_H_
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#define _MEM_INFO_HOB_H_
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#include <Uefi/UefiMultiPhase.h>
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#include <Pi/PiBootMode.h>
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#include <Pi/PiHob.h>
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#pragma pack (push, 1)
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#pragma pack (push, 1)
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extern EFI_GUID gSiMemoryS3DataGuid;
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extern EFI_GUID gSiMemoryS3DataGuid;
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@ -58,25 +62,6 @@ extern EFI_GUID gSiMemoryPlatformDataGuid;
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#define B_RANK2_PRS BIT4
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#define B_RANK2_PRS BIT4
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#define B_RANK3_PRS BIT5
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#define B_RANK3_PRS BIT5
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// @todo remove and use the MdePkg\Include\Pi\PiHob.h
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#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
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#ifndef __HOB__H__
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typedef struct _EFI_HOB_GENERIC_HEADER {
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UINT16 HobType;
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UINT16 HobLength;
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UINT32 Reserved;
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} EFI_HOB_GENERIC_HEADER;
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typedef struct _EFI_HOB_GUID_TYPE {
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EFI_HOB_GENERIC_HEADER Header;
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EFI_GUID Name;
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///
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/// Guid specific data goes here
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///
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} EFI_HOB_GUID_TYPE;
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#endif
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#endif
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///
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///
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/// Defines taken from MRC so avoid having to include MrcInterface.h
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/// Defines taken from MRC so avoid having to include MrcInterface.h
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///
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///
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@ -183,6 +168,13 @@ typedef struct {
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UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
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UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
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} MRC_CH_TIMING;
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} MRC_CH_TIMING;
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typedef struct {
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UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.
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UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.
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UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).
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UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.
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} MRC_TA_TIMING;
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///
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///
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/// Memory SMBIOS & OC Memory Data Hob
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/// Memory SMBIOS & OC Memory Data Hob
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///
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///
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@ -208,11 +200,15 @@ typedef struct {
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} CHANNEL_INFO;
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} CHANNEL_INFO;
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typedef struct {
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typedef struct {
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UINT8 Status; ///< Indicates whether this controller should be used.
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UINT8 Status; ///< Indicates whether this controller should be used.
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UINT16 DeviceId; ///< The PCI device id of this memory controller.
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UINT16 DeviceId; ///< The PCI device id of this memory controller.
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UINT8 RevisionId; ///< The PCI revision id of this memory controller.
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UINT8 RevisionId; ///< The PCI revision id of this memory controller.
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UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
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UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
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CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
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CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
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MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings
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MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings
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MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings
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MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings
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} CONTROLLER_INFO;
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} CONTROLLER_INFO;
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typedef struct {
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typedef struct {
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