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mb/intel/tglrvp: Enable Audio AIC with Max98373 & ALC5682 on TGL 

Add support for Max98373 speaker amp & ALC5682 headset codec

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I013dbc6246b07a501f9bff80c2bca3594e6cc146
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This commit is contained in:
Srinidhi N Kaushik 2020-01-24 10:43:48 -08:00 committed by Patrick Georgi
parent 04571d8dbe
commit b2ecc572de
2 changed files with 73 additions and 2 deletions
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45
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@ -91,6 +91,20 @@ chip soc/intel/tigerlake
[PchSerialIoIndexUART2] = PchSerialIoPci, [PchSerialIoIndexUART2] = PchSerialIoPci,
}" }"
#HD Audio
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHdaEnable" = "0"
register "PchHdaAudioLinkDmicEnable[0]" = "1"
register "PchHdaAudioLinkDmicEnable[1]" = "1"
register "PchHdaAudioLinkSspEnable[0]" = "1"
register "PchHdaAudioLinkSspEnable[1]" = "1"
# iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
register "PchHdaIDispLinkTmode" = "2"
# iDisp-Link Freq 4: 96MHz, 3: 48MHz.
register "PchHdaIDispLinkFrequency" = "4"
# Not disconnected/enumerable
register "PchHdaIDispCodecDisconnect" = "0"
device domain 0 on device domain 0 on
#From EDS(575683) #From EDS(575683)
device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y
@ -122,7 +136,36 @@ chip soc/intel/tigerlake
device pci 14.1 on end # USB3.1 xDCI 0xA0EE device pci 14.1 on end # USB3.1 xDCI 0xA0EE
device pci 14.2 on end # Shared RAM 0xA0EF device pci 14.2 on end # Shared RAM 0xA0EF
device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3 device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3
device pci 15.0 on end # I2C0 0xA0E8 device pci 15.0 on # I2C0 0xA0E8
chip drivers/i2c/max98373
register "vmon_slot_no" = "4"
register "imon_slot_no" = "5"
register "uid" = "0"
register "desc" = ""RIGHT SPEAKER AMP""
register "name" = ""MAXR""
device i2c 31 on end
end
chip drivers/i2c/max98373
register "vmon_slot_no" = "6"
register "imon_slot_no" = "7"
register "uid" = "1"
register "desc" = ""LEFT SPEAKER AMP""
register "name" = ""MAXL""
device i2c 32 on end
end
chip drivers/i2c/generic
register "hid" = ""10EC5682""
register "name" = ""RT58""
register "desc" = ""Realtek RT5682""
register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_C12_IRQ)"
register "probed" = "1"
# Set the jd_src to RT5668_JD1 for jack detection
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
register "property_list[0].name" = ""realtek,jd-src""
register "property_list[0].integer" = "1"
device i2c 1a on end
end
end # I2C0
device pci 15.1 on end # I2C1 0xA0E9 device pci 15.1 on end # I2C1 0xA0E9
device pci 15.2 on end # I2C2 0xA0EA device pci 15.2 on end # I2C2 0xA0EA
device pci 15.3 on end # I2C3 0xA0EB device pci 15.3 on end # I2C3 0xA0EB

30
src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
View File

@ -50,11 +50,39 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1), PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1),
PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1), PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1),
PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1), PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
/*Audio */
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SDA */
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_SCL */
PAD_CFG_GPO(GPP_C5, 1, PLTRST),
PAD_CFG_GPI_APIC(GPP_C12, NONE, PLTRST, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */
}; };
/* Early pad configuration in bootblock */ /* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
/* ToDo: Fill early gpio configurations for TPM and WWAN */
/*Audio */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_HP_SCLK */
PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_HP_SFRM */
PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S0_HP_TX */
PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S0_HP_RX */
PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* I2S1_SPKR_SCLK */
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S1_SPKR_TX */
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S1_SPKR_RX */
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S1_SPKR_SFRM */
PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), /* SNDW0_HP_CLK */
PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), /* SNDW0_HP_DATA */
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), /* SNDW1_SPKR_CLK */
PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), /* SNDW1_SPKR_DATA */
PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* DMIC1_CLK */
PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* DMIC1_DATA */
PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK */
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */
}; };
const struct pad_config *variant_gpio_table(size_t *num) const struct pad_config *variant_gpio_table(size_t *num)