Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-50

Creator:  Ronald G. Minnich <rminnich@lanl.gov>

This now boots to the point of passing the memory test in auto.c. But: we still don't have it working after the "Jumping to LinuxBIOS" step


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1966 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
arch import user (historical) 2005-07-06 17:16:23 +00:00
parent 69c79d232e
commit b2ed53dd56
4 changed files with 134 additions and 14 deletions

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@ -48,6 +48,90 @@
#define OUTC(addr, val) *(unsigned char *)(addr) = (val) #define OUTC(addr, val) *(unsigned char *)(addr) = (val)
void p4(unsigned char c){
//print_err("TRY A TX NIBLE\r\n");
__console_tx_nibble(c);
return;
print_err("now do the other\r\n");
// c = c + '0';
// if (c > '9')
// c = c + 39;
// __console_tx_byte(c);
//print_err("NO!\r\n");
// return;
switch(c) {
case 0:
print_err("0");
break;
case 1:
print_err("1");
break;
case 2:
print_err("2");
break;
case 3:
print_err("3");
break;
case 4:
print_err("4");
break;
case 5:
print_err("5");
break;
case 6:
print_err("6");
break;
case 7:
print_err("7");
break;
case 8:
print_err("8");
break;
case 9:
print_err("9");
break;
case 0xa:
print_err("a");
break;
case 0xb:
print_err("b");
break;
case 0xc:
print_err("c");
break;
case 0xd:
print_err("d");
break;
case 0xe:
print_err("e");
break;
case 0xf:
print_err("f");
break;
}
}
void p8(unsigned char c) {
/*
__console_tx_nibble(c>>4);
__console_tx_nibble(c&0xf);
*/
p4(c>>4);
p4(c&0xf);
}
void p16(unsigned short s) {
p8(s>>16);
p8(s);
}
void p32(unsigned long l) {
p16(l>>16);
p16(l);
}
/* sadly, romcc can't quite handle what we want, so we do this ugly thing */ /* sadly, romcc can't quite handle what we want, so we do this ugly thing */
#define drcctl (( volatile unsigned char *)0xfffef010) #define drcctl (( volatile unsigned char *)0xfffef010)
@ -143,6 +227,7 @@ setupsc520(void){
*cp = 4; /* uart 1 clock source */ *cp = 4; /* uart 1 clock source */
cp = (unsigned char *)0xfffefcc4; cp = (unsigned char *)0xfffefcc4;
*cp = 4; /* uart 2 clock source */ *cp = 4; /* uart 2 clock source */
#if 0
/*; set the interrupt mapping registers.*/ /*; set the interrupt mapping registers.*/
cp = (unsigned char *)0x0fffefd20; cp = (unsigned char *)0x0fffefd20;
*cp = 0x01; *cp = 0x01;
@ -172,7 +257,9 @@ setupsc520(void){
outl(0x0cf8,0x080000004); /*index the status command register on device 0*/ outl(0x0cf8,0x080000004); /*index the status command register on device 0*/
outl(0xcfc, 0x2); /*set the memory access enable bit*/ outl(0xcfc, 0x2); /*set the memory access enable bit*/
OUTC(0x0fffef072, 1); /* enable req bits in SYSARBMENB */ OUTC(0x0fffef072, 1); /* enable req bits in SYSARBMENB */
#endif
#if 0
/* set up the PAR registers as they are on the MSM586SEG */ /* set up the PAR registers as they are on the MSM586SEG */
@ -194,7 +281,7 @@ setupsc520(void){
*par++ = 0x545c00c8; /*PAR14: GP BUS MEM:CS5:Base 0xc8, size 0x5c:*/ *par++ = 0x545c00c8; /*PAR14: GP BUS MEM:CS5:Base 0xc8, size 0x5c:*/
// *par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/ // *par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/
#endif
} }
@ -285,6 +372,8 @@ int sizemem(void)
/* setup loop to do 4 external banks starting with bank 3 */ /* setup loop to do 4 external banks starting with bank 3 */
*drcbendadr=0x0ff000000; *drcbendadr=0x0ff000000;
*drcbendadr=0x0ff;
/* issue a NOP to all DRAMs */ /* issue a NOP to all DRAMs */
/* Setup DRAM control register with Disable refresh, /* Setup DRAM control register with Disable refresh,
* disable write buffer Test Mode and NOP command select * disable write buffer Test Mode and NOP command select
@ -341,10 +430,15 @@ int sizemem(void)
print_err("\r\n"); print_err("\r\n");
// continue; // continue;
} }
*drcctl = 2;
dummy_write();
*drccfg = *drccfg >> 4;
l = *drcbendadr; l = *drcbendadr;
l >>= 8; l >>= 8;
*drcbendadr = l; *drcbendadr = l;
print_err("loop around\r\n"); print_err("loop around\r\n");
*drcctl = 0;
dummy_write();
} }
#if 0 #if 0
/* enable last bank and setup ending address /* enable last bank and setup ending address
@ -588,7 +682,7 @@ bad_ram:
/* this does now work worth shit. */ /* this does now work worth shit. */
int int
staticmem(void){ staticmem(void){
volatile unsigned char *zero = (unsigned char *) 0; volatile unsigned long *zero = (unsigned long *) CACHELINESZ;
/* set up 0x18 .. **/ /* set up 0x18 .. **/
*drcbendadr = 0x88; *drcbendadr = 0x88;
*drcmctl = 0x1e; *drcmctl = 0x1e;
@ -615,9 +709,18 @@ staticmem(void){
print_err("DONE the load mode reg\r\n"); print_err("DONE the load mode reg\r\n");
/* normal mode */ /* normal mode */
*drcctl = 0x0;
*zero = 0;
print_err("DONE one last write and then turn on refresh etc\n");
*drcctl = 0x18; *drcctl = 0x18;
*zero = 0; *zero = 0;
print_err("DONE the normal\r\n"); print_err("DONE the normal\r\n");
*zero = 0xdeadbeef; *zero = 0xdeadbeef;
print_err(" zero is now "); print_err_hex32(*zero); print_err("\r\n"); if (*zero != 0xdeadbeef)
print_err("NO LUCK\r\n");
else
print_err("did a stor and load ...\r\n");
// p32(*zero);
print_err_hex32(*zero);
// print_err(" zero is now "); print_err_hex32(*zero); print_err("\r\n");
} }

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@ -2,8 +2,11 @@
## Compute the location and size of where this firmware image ## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip. ## (linuxBIOS plus bootloader) will live in the boot rom chip.
## ##
default ROM_SIZE = 512 * 1024
default FALLBACK_SIZE = 0x10000
if USE_FALLBACK_IMAGE if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE default ROM_SECTION_SIZE = 64 * 1024 # FALLBACK_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
else else
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
@ -29,7 +32,7 @@ default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
## XIP_ROM_SIZE must be a power of 2. ## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
## ##
default XIP_ROM_SIZE=65536 default XIP_ROM_SIZE=32*1024
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
## ##
@ -61,11 +64,11 @@ end
makerule ./auto.E makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ./romcc" depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end end
makerule ./auto.inc makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ./romcc" depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end end
## ##

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@ -47,17 +47,26 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void main(unsigned long bist) static void main(unsigned long bist)
{ {
volatile int i;
for(i = 0; i < 100; i++)
;
setupsc520(); setupsc520();
uart_init(); uart_init();
console_init(); console_init();
// while(1) for(i = 0; i < 100; i++)
print_err("fill usart\r\n");
// while(1)
print_err("HI THERE!\r\n"); print_err("HI THERE!\r\n");
sizemem(); // sizemem();
// staticmem(); staticmem();
while(1) // while(1)
print_err("STATIC MEM DONE\r\n"); print_err("STATIC MEM DONE\r\n");
outb(0xee, 0x80);
print_err("loop forever ...\n");
#if 0 #if 0
else { else {
@ -82,9 +91,14 @@ static void main(unsigned long bist)
dump_pci_device(PCI_DEV(0, 0, 0)); dump_pci_device(PCI_DEV(0, 0, 0));
#endif #endif
#if 1 #if 0
print_err("RAM CHECK!\r\n"); print_err("RAM CHECK!\r\n");
// Check 16MB of memory @ 0 // Check 16MB of memory @ 0
ram_check(0x00000000, 0x01000000); ram_check(0x00000000, 0x01000000);
#endif #endif
#if 1
print_err("RAM CHECK!\r\n");
// Check 1MB of memory @ 0
ram_check(0x00000000, 0x0100000);
#endif
} }

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@ -1,7 +1,7 @@
target msm586seg target msm586seg
mainboard digitallogic/msm586seg mainboard digitallogic/msm586seg
option ROM_SIZE=64*1024 option ROM_SIZE=512*1024
option DEFAULT_CONSOLE_LOGLEVEL=10 option DEFAULT_CONSOLE_LOGLEVEL=10
option MAXIMUM_CONSOLE_LOGLEVEL=10 option MAXIMUM_CONSOLE_LOGLEVEL=10
@ -14,7 +14,7 @@ option MAXIMUM_CONSOLE_LOGLEVEL=10
romimage "fallback" romimage "fallback"
option USE_FALLBACK_IMAGE=1 option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000 option ROM_IMAGE_SIZE=32 * 1024 # 0x10000
option LINUXBIOS_EXTRA_VERSION=".0Fallback" option LINUXBIOS_EXTRA_VERSION=".0Fallback"
payload /etc/hosts payload /etc/hosts
end end