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i82801gx: Fix port status in AHCI mode 

The code used PCI register 0x92 to enable sata ports,
which is wrong. The ICH7 documentation states:

"This register is only used in systems that do not
support AHCI. In AHCI enabled systems, bits[3:0] must
always be set (ICH7R only) / bits[2,0] must always be set
(Mobile only), and the status of the port is controlled
through AHCI memory space."

Writing 0x0f to ICH7-M doesn't seem to hurt, so lets write
0x0f for both variants. This patch makes sata_ahci work on
my Thinkpad T60 and X60s.

Change-Id: If3b3daec2e5fbaa446de00272ebde01cd8d52475
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/340
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Sven Schnelle 2011-10-27 13:05:40 +02:00 committed by Stefan Reinauer
parent 5e4e2290b6
commit b2f173e168
2 changed files with 9 additions and 1 deletions
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1
src/southbridge/intel/i82801gx/chip.h
View File

@ -68,6 +68,7 @@ struct southbridge_intel_i82801gx_config {
uint32_t ide_enable_primary; uint32_t ide_enable_primary;
uint32_t ide_enable_secondary; uint32_t ide_enable_secondary;
uint32_t sata_ahci; uint32_t sata_ahci;
uint32_t sata_ports_implemented;
int c4onc3_enable:1; int c4onc3_enable:1;
}; };

9
src/southbridge/intel/i82801gx/sata.c
View File

@ -30,6 +30,8 @@ static void sata_init(struct device *dev)
{ {
u32 reg32; u32 reg32;
u16 reg16; u16 reg16;
u32 *ahci_bar;
/* Get the chip configuration */ /* Get the chip configuration */
config_t *config = dev->chip_info; config_t *config = dev->chip_info;
@ -106,9 +108,14 @@ static void sata_init(struct device *dev)
/* Set Sata Controller Mode. */ /* Set Sata Controller Mode. */
pci_write_config8(dev, 0x90, 0x40); // 40=AHCI pci_write_config8(dev, 0x90, 0x40); // 40=AHCI
/* Port 0 & 1 enable */ /* In ACHI mode, bit[3:0] must always be set
* (Port status is controlled through AHCI BAR)
*/
pci_write_config8(dev, 0x92, 0x0f); pci_write_config8(dev, 0x92, 0x0f);
ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff);
ahci_bar[3] = config->sata_ports_implemented;
/* SATA Initialization register */ /* SATA Initialization register */
pci_write_config32(dev, 0x94, 0x1a000180); pci_write_config32(dev, 0x94, 0x1a000180);
} else { } else {