i82801gx: Fix port status in AHCI mode
The code used PCI register 0x92 to enable sata ports, which is wrong. The ICH7 documentation states: "This register is only used in systems that do not support AHCI. In AHCI enabled systems, bits[3:0] must always be set (ICH7R only) / bits[2,0] must always be set (Mobile only), and the status of the port is controlled through AHCI memory space." Writing 0x0f to ICH7-M doesn't seem to hurt, so lets write 0x0f for both variants. This patch makes sata_ahci work on my Thinkpad T60 and X60s. Change-Id: If3b3daec2e5fbaa446de00272ebde01cd8d52475 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/340 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -68,6 +68,7 @@ struct southbridge_intel_i82801gx_config {
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uint32_t ide_enable_primary;
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uint32_t ide_enable_secondary;
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uint32_t sata_ahci;
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uint32_t sata_ports_implemented;
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int c4onc3_enable:1;
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};
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@ -30,6 +30,8 @@ static void sata_init(struct device *dev)
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{
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u32 reg32;
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u16 reg16;
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u32 *ahci_bar;
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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@ -106,9 +108,14 @@ static void sata_init(struct device *dev)
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/* Set Sata Controller Mode. */
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pci_write_config8(dev, 0x90, 0x40); // 40=AHCI
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/* Port 0 & 1 enable */
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/* In ACHI mode, bit[3:0] must always be set
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* (Port status is controlled through AHCI BAR)
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*/
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pci_write_config8(dev, 0x92, 0x0f);
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ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff);
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ahci_bar[3] = config->sata_ports_implemented;
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/* SATA Initialization register */
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pci_write_config32(dev, 0x94, 0x1a000180);
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} else {
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