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soc/intel/cannonlake: Steal no memory for disabled IGD 

Set IgdDvmt50PreAlloc to zero if InternalGfx is disabled. It's 'correct'
to do it like this, otherwise the FSP would always allocate memory for
the IGD even if it is disabled. In addition the FSP enables the graphics
panel power even if no IGD is present which leads to a crashing FSP.
Thus, if no IGD is present we switch off the panel via UPDs.

Refer to this issue on IntelFSP for details:
https://github.com/IntelFsp/FSP/issues/49

Tested on:
* CFL platform with IGD
* CFL platform without IGD

Change-Id: I6f9e0f9855224614471d8ed23bf2a9786386ddca
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Christian Walter 2020-03-11 18:04:58 +01:00 committed by Nico Huber
parent 6670f44cd0
commit b2f8ce7591
2 changed files with 28 additions and 5 deletions
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6
Documentation/soc/intel/fsp/index.md
View File

@ -45,6 +45,11 @@ those are fixed. If possible a workaround is described here as well.
* Workaround: Disable internal UART manually after calling FSP
* Issue on public tracker: [Issue 10]
### CoffeeLakeFsp
* Disabling the internal graphics causes a crash in FSP-M
* 7.0.68.40 and older version
* Workaround: Set "tconfig->PanelPowerEnable = 0"
* Issue on public tracker: [Issue 49]
## Open Source Intel FSP specification
@ -72,4 +77,5 @@ those are fixed. If possible a workaround is described here as well.
[Issue 22]: https://github.com/IntelFsp/FSP/issues/22
[Issue 35]: https://github.com/IntelFsp/FSP/issues/35
[Issue 41]: https://github.com/IntelFsp/FSP/issues/41
[Issue 49]: https://github.com/IntelFsp/FSP/issues/49

23
src/soc/intel/cannonlake/romstage/fsp_params.c
View File

@ -2,6 +2,8 @@
/* This file is part of the coreboot project. */
#include <assert.h>
#include <device/pci_def.h>
#include <device/pci.h>
#include <cpu/x86/msr.h>
#include <console/console.h>
#include <fsp/util.h>
@ -15,14 +17,28 @@
#include "../chip.h"
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
static void soc_memory_init_params(FSPM_UPD *mupd, const config_t *config)
{
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig;
unsigned int i;
uint32_t mask = 0;
const struct device *dev = pcidev_path_on_root(PCH_DEVFN_ISH);
const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
/*
* Probe for no IGD and disable InternalGfx and panel power to prevent a
* crash in FSP-M.
*/
if (dev && dev->enabled && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) {
/* Set IGD stolen size to 64MB. */
m_cfg->InternalGfx = 1;
m_cfg->IgdDvmt50PreAlloc = 2;
} else {
m_cfg->InternalGfx = 0;
m_cfg->IgdDvmt50PreAlloc = 0;
tconfig->PanelPowerEnable = 0;
}
m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
m_cfg->SaGv = config->SaGv;
@ -71,6 +87,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
}
dev = pcidev_path_on_root(PCH_DEVFN_ISH);
/* If ISH is enabled, enable ISH elements */
if (!dev)
m_cfg->PchIshEnable = 0;
@ -122,7 +139,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig;
soc_memory_init_params(m_cfg, config);
soc_memory_init_params(mupd, config);
/* Enable SMBus controller based on config */
if (!smbus)