sb/intel/{bd82x6x|ibexpeak}: Drop p_cnt_throttling_supported
The processor P_BLK doesn't support throttling. This behaviour could be emulated with SMM, but instead just update the FADT to indicate no support for legacy I/O based throttling using P_CNT. We have _PTC defined in SSDT, which should be used in favour of P_CNT by ACPI aware OS, so this change has no effect on modern OS. Drop all occurences of p_cnt_throttling_supported and update autoport to not generate it any more. Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
parent
fa0ef81d15
commit
b30a47b841
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@ -38,7 +38,6 @@ chip northbridge/intel/sandybridge
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register "gen3_dec" = "0x001c0301"
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register "gen3_dec" = "0x001c0301"
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register "gen4_dec" = "0x00fc0701"
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register "gen4_dec" = "0x00fc0701"
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register "gpi7_routing" = "2"
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register "gpi7_routing" = "2"
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register "p_cnt_throttling_supported" = "1"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_interface_speed_support" = "0x3"
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@ -58,7 +58,6 @@ chip northbridge/intel/sandybridge
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register "gen1_dec" = "0x000c0291"
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register "gen1_dec" = "0x000c0291"
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register "gen2_dec" = "0x000c0241"
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register "gen2_dec" = "0x000c0241"
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register "gen3_dec" = "0x000c0251"
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register "gen3_dec" = "0x000c0251"
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register "p_cnt_throttling_supported" = "0"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "0"
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register "pcie_port_coalesce" = "0"
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register "sata_interface_speed_support" = "0x3"
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register "sata_interface_speed_support" = "0x3"
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@ -40,7 +40,6 @@ chip northbridge/intel/sandybridge
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chip southbridge/intel/bd82x6x
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chip southbridge/intel/bd82x6x
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register "c2_latency" = "101"
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register "c2_latency" = "101"
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register "gen1_dec" = "0x00000295" # Super I/O HWM
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register "gen1_dec" = "0x00000295" # Super I/O HWM
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register "p_cnt_throttling_supported" = "1"
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register "sata_port_map" = "0x3f"
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register "sata_port_map" = "0x3f"
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register "spi_lvscc" = "0x2005"
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register "spi_lvscc" = "0x2005"
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register "spi_uvscc" = "0x2005"
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register "spi_uvscc" = "0x2005"
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@ -40,7 +40,6 @@ chip northbridge/intel/sandybridge
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chip southbridge/intel/bd82x6x
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chip southbridge/intel/bd82x6x
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register "c2_latency" = "101"
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register "c2_latency" = "101"
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register "gen1_dec" = "0x00000295" # Super I/O HWM
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register "gen1_dec" = "0x00000295" # Super I/O HWM
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register "p_cnt_throttling_supported" = "1"
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register "sata_port_map" = "0x33"
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register "sata_port_map" = "0x33"
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register "spi_lvscc" = "0x2005"
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register "spi_lvscc" = "0x2005"
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register "spi_uvscc" = "0x2005"
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register "spi_uvscc" = "0x2005"
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@ -34,7 +34,6 @@ chip northbridge/intel/sandybridge
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register "c2_latency" = "0x0065"
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register "c2_latency" = "0x0065"
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register "docking_supported" = "0"
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register "docking_supported" = "0"
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register "gen1_dec" = "0x000c0291" # HWM
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register "gen1_dec" = "0x000c0291" # HWM
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register "p_cnt_throttling_supported" = "0"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
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register "sata_interface_speed_support" = "0x3"
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register "sata_interface_speed_support" = "0x3"
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register "sata_port_map" = "0x33"
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register "sata_port_map" = "0x33"
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@ -48,7 +48,6 @@ chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
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register "gen3_dec" = "0x000406f1"
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register "gen3_dec" = "0x000406f1"
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register "gen4_dec" = "0x000c06a1"
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register "gen4_dec" = "0x000c06a1"
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register "gpi7_routing" = "2"
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register "gpi7_routing" = "2"
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register "p_cnt_throttling_supported" = "1"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_interface_speed_support" = "0x3"
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@ -39,7 +39,6 @@ chip northbridge/intel/sandybridge
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register "sata_interface_speed_support" = "0x3"
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register "sata_interface_speed_support" = "0x3"
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register "pcie_port_coalesce" = "0"
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register "pcie_port_coalesce" = "0"
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register "p_cnt_throttling_supported" = "0"
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register "docking_supported" = "0"
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register "docking_supported" = "0"
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register "c2_latency" = "0x0065"
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register "c2_latency" = "0x0065"
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@ -66,7 +66,6 @@ chip northbridge/intel/sandybridge
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register "pcie_port_coalesce" = "1"
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register "pcie_port_coalesce" = "1"
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register "c2_latency" = "101" # c2 not supported
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register "c2_latency" = "101" # c2 not supported
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register "p_cnt_throttling_supported" = "1"
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device pci 14.0 on end # USB 3.0 Controller
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device pci 14.0 on end # USB 3.0 Controller
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.0 on end # Management Engine Interface 1
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@ -64,7 +64,6 @@ chip northbridge/intel/sandybridge
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register "pcie_port_coalesce" = "1"
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register "pcie_port_coalesce" = "1"
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register "c2_latency" = "1"
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register "c2_latency" = "1"
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register "p_cnt_throttling_supported" = "0"
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.1 off end # Management Engine Interface 2
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@ -62,7 +62,6 @@ chip northbridge/intel/sandybridge
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register "pcie_port_coalesce" = "1"
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register "pcie_port_coalesce" = "1"
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register "c2_latency" = "1"
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register "c2_latency" = "1"
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register "p_cnt_throttling_supported" = "0"
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.1 off end # Management Engine Interface 2
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@ -73,7 +73,6 @@ chip northbridge/intel/sandybridge
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register "pcie_port_coalesce" = "1"
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register "pcie_port_coalesce" = "1"
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register "c2_latency" = "1"
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register "c2_latency" = "1"
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register "p_cnt_throttling_supported" = "0"
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device pci 14.0 on end # USB 3.0 Controller
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device pci 14.0 on end # USB 3.0 Controller
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.0 on end # Management Engine Interface 1
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@ -52,7 +52,6 @@ chip northbridge/intel/sandybridge
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register "gen3_dec" = "0x00fcfe01"
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register "gen3_dec" = "0x00fcfe01"
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register "gen4_dec" = "0x000402e9"
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register "gen4_dec" = "0x000402e9"
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register "gpi6_routing" = "2"
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register "gpi6_routing" = "2"
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register "p_cnt_throttling_supported" = "1"
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register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
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register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_interface_speed_support" = "0x3"
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@ -61,7 +61,6 @@ chip northbridge/intel/sandybridge
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register "gen3_dec" = "0x00fcfe01"
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register "gen3_dec" = "0x00fcfe01"
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register "gen4_dec" = "0x007c0281"
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register "gen4_dec" = "0x007c0281"
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register "gpi6_routing" = "2"
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register "gpi6_routing" = "2"
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register "p_cnt_throttling_supported" = "1"
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register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
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register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_interface_speed_support" = "0x3"
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@ -60,7 +60,6 @@ chip northbridge/intel/sandybridge
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register "gen3_dec" = "0x00fcfe01"
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register "gen3_dec" = "0x00fcfe01"
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register "gen4_dec" = "0x000402e9"
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register "gen4_dec" = "0x000402e9"
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register "gpi6_routing" = "2"
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register "gpi6_routing" = "2"
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register "p_cnt_throttling_supported" = "1"
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register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
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register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_interface_speed_support" = "0x3"
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register "gen3_dec" = "0x00fcfe01"
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register "gen3_dec" = "0x00fcfe01"
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register "gen4_dec" = "0x000402e9"
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register "gen4_dec" = "0x000402e9"
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register "gpi6_routing" = "2"
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register "gpi6_routing" = "2"
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register "p_cnt_throttling_supported" = "1"
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register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
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register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_interface_speed_support" = "0x3"
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register "gen3_dec" = "0x00fcfe01"
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register "gen3_dec" = "0x00fcfe01"
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register "gen4_dec" = "0x000402e9"
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register "gen4_dec" = "0x000402e9"
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register "gpi6_routing" = "2"
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register "gpi6_routing" = "2"
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register "p_cnt_throttling_supported" = "1"
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register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
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register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_interface_speed_support" = "0x3"
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register "docking_supported" = "0"
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register "docking_supported" = "0"
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register "gen1_dec" = "0x00fc0601"
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register "gen1_dec" = "0x00fc0601"
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register "gen2_dec" = "0x00fc0801"
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register "gen2_dec" = "0x00fc0801"
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register "p_cnt_throttling_supported" = "1"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_interface_speed_support" = "0x3"
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@ -52,7 +52,6 @@ chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
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register "gen3_dec" = "0x00fcfe01"
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register "gen3_dec" = "0x00fcfe01"
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register "gen4_dec" = "0x000402e9"
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register "gen4_dec" = "0x000402e9"
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register "gpi6_routing" = "2"
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register "gpi6_routing" = "2"
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register "p_cnt_throttling_supported" = "1"
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register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
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register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_interface_speed_support" = "0x3"
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register "gen3_dec" = "0x00fcfe01"
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register "gen3_dec" = "0x00fcfe01"
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register "gen4_dec" = "0x000402e9"
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register "gen4_dec" = "0x000402e9"
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register "gpi6_routing" = "2"
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register "gpi6_routing" = "2"
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register "p_cnt_throttling_supported" = "1"
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register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
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register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_interface_speed_support" = "0x3"
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register "docking_supported" = "0"
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register "docking_supported" = "0"
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register "gen1_dec" = "0x00fc0601"
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register "gen1_dec" = "0x00fc0601"
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register "gen2_dec" = "0x00fc0801"
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register "gen2_dec" = "0x00fc0801"
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register "p_cnt_throttling_supported" = "1"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_interface_speed_support" = "0x3"
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register "gen3_dec" = "0x003c0701"
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register "gen3_dec" = "0x003c0701"
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register "c2_latency" = "1"
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register "c2_latency" = "1"
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register "p_cnt_throttling_supported" = "0"
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.1 off end # Management Engine Interface 2
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@ -40,7 +40,6 @@ chip northbridge/intel/sandybridge
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register "pcie_port_coalesce" = "0"
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register "pcie_port_coalesce" = "0"
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register "c2_latency" = "101" # c2 not supported
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register "c2_latency" = "101" # c2 not supported
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register "p_cnt_throttling_supported" = "1"
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register "xhci_switchable_ports" = "0x0f"
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register "xhci_switchable_ports" = "0x0f"
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register "superspeed_capable_ports" = "0x0f"
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register "superspeed_capable_ports" = "0x0f"
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@ -46,7 +46,6 @@ chip northbridge/intel/sandybridge
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register "gen4_dec" = "0x00000000"
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register "gen4_dec" = "0x00000000"
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register "gpi13_routing" = "2"
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register "gpi13_routing" = "2"
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register "gpi6_routing" = "2"
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register "gpi6_routing" = "2"
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register "p_cnt_throttling_supported" = "1"
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register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 1, 0, 0, 0 }"
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register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 1, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_interface_speed_support" = "0x3"
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register "gen4_dec" = "0x000c06a1"
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register "gen4_dec" = "0x000c06a1"
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register "gpi13_routing" = "2"
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register "gpi13_routing" = "2"
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register "gpi7_routing" = "2"
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register "gpi7_routing" = "2"
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register "p_cnt_throttling_supported" = "1"
|
|
||||||
register "pcie_hotplug_map" = "{ 0, 1, 0, 1, 0, 0, 0, 0 }"
|
register "pcie_hotplug_map" = "{ 0, 1, 0, 1, 0, 0, 0, 0 }"
|
||||||
register "pcie_port_coalesce" = "1"
|
register "pcie_port_coalesce" = "1"
|
||||||
register "sata_interface_speed_support" = "0x3"
|
register "sata_interface_speed_support" = "0x3"
|
||||||
|
|
|
@ -68,7 +68,6 @@ chip northbridge/intel/sandybridge
|
||||||
# Enable zero-based linear PCIe root port functions
|
# Enable zero-based linear PCIe root port functions
|
||||||
register "pcie_port_coalesce" = "1"
|
register "pcie_port_coalesce" = "1"
|
||||||
register "c2_latency" = "101" # c2 not supported
|
register "c2_latency" = "101" # c2 not supported
|
||||||
register "p_cnt_throttling_supported" = "1"
|
|
||||||
|
|
||||||
# device specific SPI configuration
|
# device specific SPI configuration
|
||||||
register "spi_uvscc" = "0x2005"
|
register "spi_uvscc" = "0x2005"
|
||||||
|
|
|
@ -68,7 +68,6 @@ chip northbridge/intel/sandybridge
|
||||||
register "pcie_port_coalesce" = "1"
|
register "pcie_port_coalesce" = "1"
|
||||||
|
|
||||||
register "c2_latency" = "101" # c2 not supported
|
register "c2_latency" = "101" # c2 not supported
|
||||||
register "p_cnt_throttling_supported" = "1"
|
|
||||||
|
|
||||||
register "spi_uvscc" = "0x2005"
|
register "spi_uvscc" = "0x2005"
|
||||||
register "spi_lvscc" = "0x2005"
|
register "spi_lvscc" = "0x2005"
|
||||||
|
|
|
@ -39,7 +39,6 @@ chip northbridge/intel/sandybridge
|
||||||
register "gen3_dec" = "0x000c06a1"
|
register "gen3_dec" = "0x000c06a1"
|
||||||
register "gpi13_routing" = "2"
|
register "gpi13_routing" = "2"
|
||||||
register "gpi1_routing" = "2"
|
register "gpi1_routing" = "2"
|
||||||
register "p_cnt_throttling_supported" = "1"
|
|
||||||
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
|
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
|
||||||
register "pcie_port_coalesce" = "1"
|
register "pcie_port_coalesce" = "1"
|
||||||
register "sata_interface_speed_support" = "0x3"
|
register "sata_interface_speed_support" = "0x3"
|
||||||
|
|
|
@ -71,7 +71,6 @@ chip northbridge/intel/sandybridge
|
||||||
# Enable zero-based linear PCIe root port functions
|
# Enable zero-based linear PCIe root port functions
|
||||||
register "pcie_port_coalesce" = "1"
|
register "pcie_port_coalesce" = "1"
|
||||||
register "c2_latency" = "101" # c2 not supported
|
register "c2_latency" = "101" # c2 not supported
|
||||||
register "p_cnt_throttling_supported" = "1"
|
|
||||||
register "docking_supported" = "1"
|
register "docking_supported" = "1"
|
||||||
|
|
||||||
register "spi_uvscc" = "0x2005"
|
register "spi_uvscc" = "0x2005"
|
||||||
|
|
|
@ -63,7 +63,6 @@ chip northbridge/intel/sandybridge
|
||||||
register "pcie_port_coalesce" = "1"
|
register "pcie_port_coalesce" = "1"
|
||||||
|
|
||||||
register "c2_latency" = "101" # c2 not supported
|
register "c2_latency" = "101" # c2 not supported
|
||||||
register "p_cnt_throttling_supported" = "1"
|
|
||||||
|
|
||||||
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
|
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
|
||||||
|
|
||||||
|
|
|
@ -63,7 +63,6 @@ chip northbridge/intel/sandybridge
|
||||||
register "pcie_port_coalesce" = "1"
|
register "pcie_port_coalesce" = "1"
|
||||||
|
|
||||||
register "c2_latency" = "101" # c2 not supported
|
register "c2_latency" = "101" # c2 not supported
|
||||||
register "p_cnt_throttling_supported" = "1"
|
|
||||||
|
|
||||||
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
|
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
|
||||||
|
|
||||||
|
|
|
@ -62,7 +62,6 @@ chip northbridge/intel/sandybridge
|
||||||
# Enable zero-based linear PCIe root port functions
|
# Enable zero-based linear PCIe root port functions
|
||||||
register "pcie_port_coalesce" = "1"
|
register "pcie_port_coalesce" = "1"
|
||||||
register "c2_latency" = "101" # c2 not supported
|
register "c2_latency" = "101" # c2 not supported
|
||||||
register "p_cnt_throttling_supported" = "1"
|
|
||||||
|
|
||||||
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
|
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
|
||||||
|
|
||||||
|
|
|
@ -51,7 +51,6 @@ chip northbridge/intel/sandybridge
|
||||||
register "gen1_dec" = "0x007c1601"
|
register "gen1_dec" = "0x007c1601"
|
||||||
register "gen2_dec" = "0x000c15e1"
|
register "gen2_dec" = "0x000c15e1"
|
||||||
register "gen4_dec" = "0x000c06a1"
|
register "gen4_dec" = "0x000c06a1"
|
||||||
register "p_cnt_throttling_supported" = "1"
|
|
||||||
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
|
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
|
||||||
register "pcie_port_coalesce" = "1"
|
register "pcie_port_coalesce" = "1"
|
||||||
register "sata_interface_speed_support" = "0x3"
|
register "sata_interface_speed_support" = "0x3"
|
||||||
|
|
|
@ -66,7 +66,6 @@ chip northbridge/intel/sandybridge
|
||||||
# Enable zero-based linear PCIe root port functions
|
# Enable zero-based linear PCIe root port functions
|
||||||
register "pcie_port_coalesce" = "1"
|
register "pcie_port_coalesce" = "1"
|
||||||
register "c2_latency" = "0x0065"
|
register "c2_latency" = "0x0065"
|
||||||
register "p_cnt_throttling_supported" = "1"
|
|
||||||
|
|
||||||
register "spi_uvscc" = "0x2005"
|
register "spi_uvscc" = "0x2005"
|
||||||
register "spi_lvscc" = "0x2005"
|
register "spi_lvscc" = "0x2005"
|
||||||
|
|
|
@ -70,7 +70,6 @@ chip northbridge/intel/sandybridge
|
||||||
# Enable zero-based linear PCIe root port functions
|
# Enable zero-based linear PCIe root port functions
|
||||||
register "pcie_port_coalesce" = "1"
|
register "pcie_port_coalesce" = "1"
|
||||||
register "c2_latency" = "101" # c2 not supported
|
register "c2_latency" = "101" # c2 not supported
|
||||||
register "p_cnt_throttling_supported" = "1"
|
|
||||||
|
|
||||||
register "spi_uvscc" = "0x2005"
|
register "spi_uvscc" = "0x2005"
|
||||||
register "spi_lvscc" = "0x2005"
|
register "spi_lvscc" = "0x2005"
|
||||||
|
|
|
@ -68,7 +68,6 @@ chip northbridge/intel/nehalem
|
||||||
register "gen3_dec" = "0x1c1681"
|
register "gen3_dec" = "0x1c1681"
|
||||||
register "gen4_dec" = "0x040069"
|
register "gen4_dec" = "0x040069"
|
||||||
|
|
||||||
register "p_cnt_throttling_supported" = "1"
|
|
||||||
register "c2_latency" = "1"
|
register "c2_latency" = "1"
|
||||||
register "docking_supported" = "1"
|
register "docking_supported" = "1"
|
||||||
|
|
||||||
|
|
|
@ -69,7 +69,6 @@ chip northbridge/intel/sandybridge
|
||||||
register "pcie_port_coalesce" = "1"
|
register "pcie_port_coalesce" = "1"
|
||||||
|
|
||||||
register "c2_latency" = "101" # c2 not supported
|
register "c2_latency" = "101" # c2 not supported
|
||||||
register "p_cnt_throttling_supported" = "1"
|
|
||||||
|
|
||||||
register "spi_uvscc" = "0x2005"
|
register "spi_uvscc" = "0x2005"
|
||||||
register "spi_lvscc" = "0x2005"
|
register "spi_lvscc" = "0x2005"
|
||||||
|
|
|
@ -72,7 +72,6 @@ chip northbridge/intel/sandybridge
|
||||||
# Enable zero-based linear PCIe root port functions
|
# Enable zero-based linear PCIe root port functions
|
||||||
register "pcie_port_coalesce" = "1"
|
register "pcie_port_coalesce" = "1"
|
||||||
register "c2_latency" = "101" # c2 not supported
|
register "c2_latency" = "101" # c2 not supported
|
||||||
register "p_cnt_throttling_supported" = "1"
|
|
||||||
|
|
||||||
register "spi_uvscc" = "0x2005"
|
register "spi_uvscc" = "0x2005"
|
||||||
register "spi_lvscc" = "0x2005"
|
register "spi_lvscc" = "0x2005"
|
||||||
|
|
|
@ -21,7 +21,6 @@ chip northbridge/intel/sandybridge
|
||||||
register "docking_supported" = "0"
|
register "docking_supported" = "0"
|
||||||
register "gen1_dec" = "0x000c0291"
|
register "gen1_dec" = "0x000c0291"
|
||||||
register "gen2_dec" = "0x000c0a01"
|
register "gen2_dec" = "0x000c0a01"
|
||||||
register "p_cnt_throttling_supported" = "1"
|
|
||||||
register "pcie_port_coalesce" = "1"
|
register "pcie_port_coalesce" = "1"
|
||||||
register "sata_interface_speed_support" = "0x3"
|
register "sata_interface_speed_support" = "0x3"
|
||||||
register "sata_port_map" = "0x33"
|
register "sata_port_map" = "0x33"
|
||||||
|
|
|
@ -66,7 +66,6 @@ chip northbridge/intel/sandybridge
|
||||||
register "pcie_port_coalesce" = "0"
|
register "pcie_port_coalesce" = "0"
|
||||||
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
|
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
|
||||||
|
|
||||||
register "p_cnt_throttling_supported" = "1"
|
|
||||||
|
|
||||||
register "xhci_overcurrent_mapping" = "0x00080401"
|
register "xhci_overcurrent_mapping" = "0x00080401"
|
||||||
register "xhci_switchable_ports" = "0x0f"
|
register "xhci_switchable_ports" = "0x0f"
|
||||||
|
|
|
@ -71,7 +71,6 @@ chip northbridge/intel/sandybridge
|
||||||
register "pcie_port_coalesce" = "0"
|
register "pcie_port_coalesce" = "0"
|
||||||
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 1, 1 }"
|
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 1, 1 }"
|
||||||
|
|
||||||
register "p_cnt_throttling_supported" = "1"
|
|
||||||
|
|
||||||
register "xhci_overcurrent_mapping" = "0x00000c03"
|
register "xhci_overcurrent_mapping" = "0x00000c03"
|
||||||
register "xhci_switchable_ports" = "0x0f"
|
register "xhci_switchable_ports" = "0x0f"
|
||||||
|
|
|
@ -64,7 +64,6 @@ chip northbridge/intel/sandybridge
|
||||||
register "gen3_dec" = "0x00fc1601"
|
register "gen3_dec" = "0x00fc1601"
|
||||||
|
|
||||||
register "c2_latency" = "1"
|
register "c2_latency" = "1"
|
||||||
register "p_cnt_throttling_supported" = "0"
|
|
||||||
|
|
||||||
device pci 16.0 on end # Management Engine Interface 1
|
device pci 16.0 on end # Management Engine Interface 1
|
||||||
device pci 16.1 off end # Management Engine Interface 2
|
device pci 16.1 off end # Management Engine Interface 2
|
||||||
|
|
|
@ -48,7 +48,6 @@ chip northbridge/intel/sandybridge
|
||||||
register "sata_port_map" = "0x3"
|
register "sata_port_map" = "0x3"
|
||||||
|
|
||||||
register "c2_latency" = "1"
|
register "c2_latency" = "1"
|
||||||
register "p_cnt_throttling_supported" = "0"
|
|
||||||
|
|
||||||
register "gen1_dec" = "0x00fc1601"
|
register "gen1_dec" = "0x00fc1601"
|
||||||
# SuperIO range is 0x700-0x73f
|
# SuperIO range is 0x700-0x73f
|
||||||
|
|
|
@ -50,7 +50,6 @@ chip northbridge/intel/sandybridge
|
||||||
register "gen2_dec" = "0x000c0a01"
|
register "gen2_dec" = "0x000c0a01"
|
||||||
register "gen3_dec" = "0x00000000"
|
register "gen3_dec" = "0x00000000"
|
||||||
register "gen4_dec" = "0x00000000"
|
register "gen4_dec" = "0x00000000"
|
||||||
register "p_cnt_throttling_supported" = "0"
|
|
||||||
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
|
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
|
||||||
register "pcie_port_coalesce" = "1"
|
register "pcie_port_coalesce" = "1"
|
||||||
register "sata_interface_speed_support" = "0x3"
|
register "sata_interface_speed_support" = "0x3"
|
||||||
|
|
|
@ -82,7 +82,6 @@ struct southbridge_intel_bd82x6x_config {
|
||||||
uint8_t pcie_aspm_f6;
|
uint8_t pcie_aspm_f6;
|
||||||
uint8_t pcie_aspm_f7;
|
uint8_t pcie_aspm_f7;
|
||||||
|
|
||||||
int p_cnt_throttling_supported;
|
|
||||||
int c2_latency;
|
int c2_latency;
|
||||||
int docking_supported;
|
int docking_supported;
|
||||||
|
|
||||||
|
|
|
@ -768,12 +768,10 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
|
||||||
fadt->p_lvl3_lat = 87;
|
fadt->p_lvl3_lat = 87;
|
||||||
fadt->flush_size = 1024;
|
fadt->flush_size = 1024;
|
||||||
fadt->flush_stride = 16;
|
fadt->flush_stride = 16;
|
||||||
fadt->duty_offset = 1;
|
/* P_CNT not supported */
|
||||||
if (chip->p_cnt_throttling_supported) {
|
fadt->duty_offset = 0;
|
||||||
fadt->duty_width = 3;
|
fadt->duty_width = 0;
|
||||||
} else {
|
|
||||||
fadt->duty_width = 0;
|
|
||||||
}
|
|
||||||
fadt->day_alrm = 0xd;
|
fadt->day_alrm = 0xd;
|
||||||
fadt->mon_alrm = 0x00;
|
fadt->mon_alrm = 0x00;
|
||||||
fadt->century = 0x00;
|
fadt->century = 0x00;
|
||||||
|
|
|
@ -680,12 +680,10 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
|
||||||
fadt->p_lvl3_lat = 87;
|
fadt->p_lvl3_lat = 87;
|
||||||
fadt->flush_size = 1024;
|
fadt->flush_size = 1024;
|
||||||
fadt->flush_stride = 16;
|
fadt->flush_stride = 16;
|
||||||
fadt->duty_offset = 1;
|
/* P_CNT not supported */
|
||||||
if (chip->p_cnt_throttling_supported) {
|
fadt->duty_offset = 0;
|
||||||
fadt->duty_width = 3;
|
fadt->duty_width = 0;
|
||||||
} else {
|
|
||||||
fadt->duty_width = 0;
|
|
||||||
}
|
|
||||||
fadt->day_alrm = 0xd;
|
fadt->day_alrm = 0xd;
|
||||||
fadt->mon_alrm = 0x00;
|
fadt->mon_alrm = 0x00;
|
||||||
fadt->century = 0x32;
|
fadt->century = 0x32;
|
||||||
|
|
|
@ -233,7 +233,6 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
|
||||||
|
|
||||||
"sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f),
|
"sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f),
|
||||||
|
|
||||||
"p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)),
|
|
||||||
"c2_latency": FormatHexLE16(FADT[96:98]),
|
"c2_latency": FormatHexLE16(FADT[96:98]),
|
||||||
"docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)),
|
"docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)),
|
||||||
"spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]),
|
"spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]),
|
||||||
|
|
Loading…
Reference in New Issue