amdfam10 boards: Drop array bus_sp5100

Only bus_sp5100[0] is evaluated.

Change-Id: I42a5040ea70a84fb674f2c616c6eba7b23dcdc29
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2019-01-03 11:38:59 +02:00
parent 21c60fa2b2
commit b30e2bfe34
9 changed files with 10 additions and 54 deletions

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@ -25,7 +25,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
u8 bus_sp5100[2];
u32 apicid_sp5100;
/*
@ -50,7 +49,6 @@ u32 hcdnx[] = {
void get_bus_conf(void)
{
u32 apicid_base;
struct device *dev;
int i;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
@ -63,17 +61,7 @@ void get_bus_conf(void)
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
for (i = 0; i < 2; i++) {
bus_sp5100[i] = 0;
}
bus_sp5100[0] = (sysconf.pci1234[0] >> 16) & 0xff;
/* sp5100 */
dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(0x14, 4));
if (dev) {
bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))

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@ -60,7 +60,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
pirq_info->rfu = rfu;
}
extern u8 bus_sp5100[2];
unsigned long write_pirq_routing_table(unsigned long addr)
{
@ -86,7 +85,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->version = PIRQ_VERSION;
/* Where the interrupt router resides */
pirq->rtr_bus = bus_sp5100[0];
pirq->rtr_bus = pirq_router_bus;
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
pirq->exclusive_irqs = 0;
@ -102,7 +101,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num = 0;
/* pci bridge */
write_pirq_info(pirq_info, bus_sp5100[0],
write_pirq_info(pirq_info, pirq_router_bus,
PCI_DEVFN(0x14, 4), LNKA, IRQBM, LNKB,
IRQBM, LNKC, IRQBM, LNKD, IRQBM, 0, 0);
pirq_info++;

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@ -21,8 +21,6 @@
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
extern u8 bus_sp5100[2];
extern u32 apicid_sp5100;

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@ -25,7 +25,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
u8 bus_sp5100[2];
u32 apicid_sp5100;
/*
@ -50,7 +49,6 @@ u32 hcdnx[] = {
void get_bus_conf(void)
{
u32 apicid_base;
struct device *dev;
int i;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
@ -63,17 +61,7 @@ void get_bus_conf(void)
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
for (i = 0; i < 2; i++) {
bus_sp5100[i] = 0;
}
bus_sp5100[0] = (sysconf.pci1234[0] >> 16) & 0xff;
/* sp5100 */
dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(0x14, 4));
if (dev) {
bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))

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@ -60,8 +60,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
pirq_info->rfu = rfu;
}
extern u8 bus_sp5100[2];
unsigned long write_pirq_routing_table(unsigned long addr)
{
struct irq_routing_table *pirq;
@ -86,7 +84,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->version = PIRQ_VERSION;
/* Where the interrupt router resides */
pirq->rtr_bus = bus_sp5100[0];
pirq->rtr_bus = pirq_router_bus;
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
pirq->exclusive_irqs = 0;
@ -102,7 +100,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num = 0;
/* pci bridge */
write_pirq_info(pirq_info, bus_sp5100[0],
write_pirq_info(pirq_info, pirq_router_bus,
PCI_DEVFN(0x14, 4), LNKA, IRQBM, LNKB,
IRQBM, LNKC, IRQBM, LNKD, IRQBM, 0, 0);
pirq_info++;

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@ -21,8 +21,6 @@
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
extern u8 bus_sp5100[2];
extern u32 apicid_sp5100;

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@ -25,7 +25,6 @@
* and acpi_tables busnum is default.
*/
u8 bus_sr5650[14];
u8 bus_sp5100[2];
u32 apicid_sp5100;
/*
@ -63,23 +62,13 @@ void get_bus_conf(void)
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
for (i = 0; i < 2; i++) {
bus_sp5100[i] = 0;
}
for (i = 0; i < ARRAY_SIZE(bus_sr5650); i++) {
bus_sr5650[i] = 0;
}
bus_sr5650[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_sp5100[0] = bus_sr5650[0];
/* sp5100 */
dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(0x14, 4));
if (dev) {
bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
pirq_router_bus = bus_sr5650[0];
/* sr5650 */
for (i = 1; i < ARRAY_SIZE(bus_sr5650); i++) {

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@ -40,7 +40,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
pirq_info->rfu = rfu;
}
extern u8 bus_sp5100[2];
unsigned long write_pirq_routing_table(unsigned long addr)
{
@ -65,7 +64,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_sp5100[0];
pirq->rtr_bus = pirq_router_bus;
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
pirq->exclusive_irqs = 0;
@ -81,7 +80,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num = 0;
/* pci bridge */
write_pirq_info(pirq_info, bus_sp5100[0],
write_pirq_info(pirq_info, pirq_router_bus,
PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2,
0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++;

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@ -21,7 +21,6 @@
#include <cpu/amd/amdfam10_sysconf.h>
extern u8 bus_sr5650[14];
extern u8 bus_sp5100[2];
extern u32 apicid_sp5100;
@ -49,7 +48,7 @@ static void *smp_write_config_table(void *v)
u32 *dword;
u8 byte;
dev = dev_find_slot(0, //bus_sp5100[0], TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0.
dev = dev_find_slot(0, //pirq_router_bus TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0.
PCI_DEVFN(0x14, 0));
if (dev) {
dword = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0);