GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/tigerlake: Remove MIPI clock setting from devicetree 

In Tiger Lake we have support for enabling MIPI clocks at runtime in
ACPI. Hence remove setting pch_islclk from devcietree and chip.h.
Also update functions which reference pch_isclk.

BUG=b:148884060
Branch=None
Test=build and boot volteer and verify camera functionality

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I6b3399172c43b4afa4267873ddd8ccf8d417ca16
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41570
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Srinidhi N Kaushik 2020-05-20 11:55:36 -07:00 committed by Patrick Georgi
parent b4d7116a74
commit b30fe36734
3 changed files with 0 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
View File

@ -32,9 +32,6 @@ chip soc/intel/tigerlake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 Camera register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 Camera
# Enable Pch iSCLK
register "pch_isclk" = "1"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801" register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201" register "gen2_dec" = "0x000c0201"

3
src/soc/intel/tigerlake/chip.h
View File

@ -206,9 +206,6 @@ struct soc_intel_tigerlake_config {
DEBUG_INTERFACE_TRACEHUB = (1 << 5), DEBUG_INTERFACE_TRACEHUB = (1 << 5),
} debug_interface_flag; } debug_interface_flag;
/* Enable Pch iSCLK */
uint8_t pch_isclk;
/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
enum { enum {
FORCE_DISABLE, FORCE_DISABLE,

20
src/soc/intel/tigerlake/finalize.c
View File

@ -27,24 +27,6 @@
#include <soc/soc_chip.h> #include <soc/soc_chip.h>
#include <soc/systemagent.h> #include <soc/systemagent.h>
#define CAMERA1_CLK 0x8000 /* Camera 1 Clock */
#define CAMERA2_CLK 0x8080 /* Camera 2 Clock */
#define CAM_CLK_EN (1 << 1)
#define MIPI_CLK (1 << 0)
#define HDPLL_CLK (0 << 0)
static void pch_enable_isclk(void)
{
pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK);
pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK);
}
static void pch_handle_sideband(config_t *config)
{
if (config->pch_isclk)
pch_enable_isclk();
}
static void pch_finalize(void) static void pch_finalize(void)
{ {
uint32_t reg32; uint32_t reg32;
@ -83,8 +65,6 @@ static void pch_finalize(void)
write32(pmcbase + CPPMVRIC, reg32); write32(pmcbase + CPPMVRIC, reg32);
} }
pch_handle_sideband(config);
pmc_clear_pmcon_sts(); pmc_clear_pmcon_sts();
} }