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nb/intel/nehalem: Hide some raminit output messages 

Hide some debug output behind CONFIG_DEBUG_RAM_SETUP. That way the
pre-ram console does not overflow.

Change-Id: Idc425f4d10443f6ee7f9b4da67eb6542069cc40c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans 2019-04-14 17:53:28 +02:00 committed by Martin Roth
parent 4c15ea5bab
commit b328209330
2 changed files with 19 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/northbridge/intel/nehalem/Kconfig
View File

@ -23,6 +23,7 @@ config NORTHBRIDGE_INTEL_NEHALEM
select CACHE_MRC_SETTINGS select CACHE_MRC_SETTINGS
select POSTCAR_STAGE select POSTCAR_STAGE
select POSTCAR_CONSOLE select POSTCAR_CONSOLE
select HAVE_DEBUG_RAM_SETUP
if NORTHBRIDGE_INTEL_NEHALEM if NORTHBRIDGE_INTEL_NEHALEM

34
src/northbridge/intel/nehalem/raminit.c
View File

@ -1568,14 +1568,14 @@ static void write_training_data(struct raminfo *info)
static void dump_timings(struct raminfo *info) static void dump_timings(struct raminfo *info)
{ {
int channel, slot, rank, lane, i; int channel, slot, rank, lane, i;
printk(BIOS_DEBUG, "Timings:\n"); printk(RAM_DEBUG, "Timings:\n");
FOR_POPULATED_RANKS { FOR_POPULATED_RANKS {
printk(BIOS_DEBUG, "channel %d, slot %d, rank %d\n", channel, printk(RAM_DEBUG, "channel %d, slot %d, rank %d\n", channel,
slot, rank); slot, rank);
for (lane = 0; lane < 9; lane++) { for (lane = 0; lane < 9; lane++) {
printk(BIOS_DEBUG, "lane %d: ", lane); printk(RAM_DEBUG, "lane %d: ", lane);
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
printk(BIOS_DEBUG, "%x (%x) ", printk(RAM_DEBUG, "%x (%x) ",
read_500(info, channel, read_500(info, channel,
get_timing_register_addr get_timing_register_addr
(lane, i, slot, rank), (lane, i, slot, rank),
@ -1584,12 +1584,12 @@ static void dump_timings(struct raminfo *info)
lane_timings[i][channel][slot][rank] lane_timings[i][channel][slot][rank]
[lane]); [lane]);
} }
printk(BIOS_DEBUG, "\n"); printk(RAM_DEBUG, "\n");
} }
} }
printk(BIOS_DEBUG, "[178] = %x (%x)\n", read_1d0(0x178, 7), printk(RAM_DEBUG, "[178] = %x (%x)\n", read_1d0(0x178, 7),
info->training.reg_178); info->training.reg_178);
printk(BIOS_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6), printk(RAM_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6),
info->training.reg_10b); info->training.reg_10b);
} }
@ -1623,8 +1623,8 @@ static void save_timings(struct raminfo *info)
train.reg_6dc = MCHBAR32(0x6dc); train.reg_6dc = MCHBAR32(0x6dc);
train.reg_6e8 = MCHBAR32(0x6e8); train.reg_6e8 = MCHBAR32(0x6e8);
printk (BIOS_SPEW, "[6dc] = %x\n", train.reg_6dc); printk(RAM_SPEW, "[6dc] = %x\n", train.reg_6dc);
printk (BIOS_SPEW, "[6e8] = %x\n", train.reg_6e8); printk(RAM_SPEW, "[6e8] = %x\n", train.reg_6e8);
/* Save the MRC S3 restore data to cbmem */ /* Save the MRC S3 restore data to cbmem */
mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION,
@ -3403,7 +3403,7 @@ set_6d_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2,
0, 1, &ratios2); 0, 1, &ratios2);
compute_frequence_ratios(info, freq1, freq2, num_cycles_3, num_cycles_4, compute_frequence_ratios(info, freq1, freq2, num_cycles_3, num_cycles_4,
0, 1, &ratios1); 0, 1, &ratios1);
printk (BIOS_SPEW, "[%x] <= %x\n", reg, printk(RAM_SPEW, "[%x] <= %x\n", reg,
ratios1.freq4_to_max_remainder | (ratios2. ratios1.freq4_to_max_remainder | (ratios2.
freq4_to_max_remainder freq4_to_max_remainder
<< 8) << 8)
@ -3486,7 +3486,8 @@ static void set_2dxx_series(struct raminfo *info, int s3resume)
frequency_11(info) / 2, 4000, 4000, 0, 0); frequency_11(info) / 2, 4000, 4000, 0, 0);
if (s3resume) { if (s3resume) {
printk (BIOS_SPEW, "[6dc] <= %x\n", info->cached_training->reg_6dc); printk(RAM_SPEW, "[6dc] <= %x\n",
info->cached_training->reg_6dc);
MCHBAR32(0x6dc) = info->cached_training->reg_6dc; MCHBAR32(0x6dc) = info->cached_training->reg_6dc;
} else } else
set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11(info), 0, set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11(info), 0,
@ -3497,7 +3498,8 @@ static void set_2dxx_series(struct raminfo *info, int s3resume)
set_2dx8_reg(info, 0x6e4, 1, 2 * info->fsb_frequency, set_2dx8_reg(info, 0x6e4, 1, 2 * info->fsb_frequency,
frequency_11(info) / 2, 3500, 0, 0, 0); frequency_11(info) / 2, 3500, 0, 0, 0);
if (s3resume) { if (s3resume) {
printk (BIOS_SPEW, "[6e8] <= %x\n", info->cached_training->reg_6e8); printk(RAM_SPEW, "[6e8] <= %x\n",
info->cached_training->reg_6e8);
MCHBAR32(0x6e8) = info->cached_training->reg_6e8; MCHBAR32(0x6e8) = info->cached_training->reg_6e8;
} else } else
set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11(info), 0, set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11(info), 0,
@ -4026,19 +4028,19 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
int j; int j;
if (s3resume && info.cached_training) { if (s3resume && info.cached_training) {
restore_274265(&info); restore_274265(&info);
printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", printk(RAM_DEBUG, "reg2ca9_bit0 = %x\n",
info.cached_training->reg2ca9_bit0); info.cached_training->reg2ca9_bit0);
for (i = 0; i < 2; i++) for (i = 0; i < 2; i++)
for (j = 0; j < 3; j++) for (j = 0; j < 3; j++)
printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n",
i, j, info.cached_training->reg274265[i][j]); i, j, info.cached_training->reg274265[i][j]);
} else { } else {
set_274265(&info); set_274265(&info);
printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", printk(RAM_DEBUG, "reg2ca9_bit0 = %x\n",
info.training.reg2ca9_bit0); info.training.reg2ca9_bit0);
for (i = 0; i < 2; i++) for (i = 0; i < 2; i++)
for (j = 0; j < 3; j++) for (j = 0; j < 3; j++)
printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n",
i, j, info.training.reg274265[i][j]); i, j, info.training.reg274265[i][j]);
} }