nb/intel/nehalem: Hide some raminit output messages
Hide some debug output behind CONFIG_DEBUG_RAM_SETUP. That way the pre-ram console does not overflow. Change-Id: Idc425f4d10443f6ee7f9b4da67eb6542069cc40c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -23,6 +23,7 @@ config NORTHBRIDGE_INTEL_NEHALEM
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select CACHE_MRC_SETTINGS
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select POSTCAR_STAGE
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select POSTCAR_CONSOLE
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select HAVE_DEBUG_RAM_SETUP
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if NORTHBRIDGE_INTEL_NEHALEM
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@ -1568,14 +1568,14 @@ static void write_training_data(struct raminfo *info)
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static void dump_timings(struct raminfo *info)
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{
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int channel, slot, rank, lane, i;
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printk(BIOS_DEBUG, "Timings:\n");
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printk(RAM_DEBUG, "Timings:\n");
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FOR_POPULATED_RANKS {
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printk(BIOS_DEBUG, "channel %d, slot %d, rank %d\n", channel,
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printk(RAM_DEBUG, "channel %d, slot %d, rank %d\n", channel,
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slot, rank);
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for (lane = 0; lane < 9; lane++) {
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printk(BIOS_DEBUG, "lane %d: ", lane);
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printk(RAM_DEBUG, "lane %d: ", lane);
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for (i = 0; i < 4; i++) {
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printk(BIOS_DEBUG, "%x (%x) ",
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printk(RAM_DEBUG, "%x (%x) ",
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read_500(info, channel,
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get_timing_register_addr
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(lane, i, slot, rank),
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@ -1584,12 +1584,12 @@ static void dump_timings(struct raminfo *info)
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lane_timings[i][channel][slot][rank]
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[lane]);
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}
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printk(BIOS_DEBUG, "\n");
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printk(RAM_DEBUG, "\n");
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}
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}
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printk(BIOS_DEBUG, "[178] = %x (%x)\n", read_1d0(0x178, 7),
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printk(RAM_DEBUG, "[178] = %x (%x)\n", read_1d0(0x178, 7),
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info->training.reg_178);
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printk(BIOS_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6),
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printk(RAM_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6),
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info->training.reg_10b);
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}
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@ -1623,8 +1623,8 @@ static void save_timings(struct raminfo *info)
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train.reg_6dc = MCHBAR32(0x6dc);
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train.reg_6e8 = MCHBAR32(0x6e8);
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printk (BIOS_SPEW, "[6dc] = %x\n", train.reg_6dc);
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printk (BIOS_SPEW, "[6e8] = %x\n", train.reg_6e8);
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printk(RAM_SPEW, "[6dc] = %x\n", train.reg_6dc);
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printk(RAM_SPEW, "[6e8] = %x\n", train.reg_6e8);
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/* Save the MRC S3 restore data to cbmem */
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mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION,
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@ -3403,7 +3403,7 @@ set_6d_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2,
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0, 1, &ratios2);
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compute_frequence_ratios(info, freq1, freq2, num_cycles_3, num_cycles_4,
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0, 1, &ratios1);
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printk (BIOS_SPEW, "[%x] <= %x\n", reg,
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printk(RAM_SPEW, "[%x] <= %x\n", reg,
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ratios1.freq4_to_max_remainder | (ratios2.
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freq4_to_max_remainder
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<< 8)
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@ -3486,7 +3486,8 @@ static void set_2dxx_series(struct raminfo *info, int s3resume)
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frequency_11(info) / 2, 4000, 4000, 0, 0);
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if (s3resume) {
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printk (BIOS_SPEW, "[6dc] <= %x\n", info->cached_training->reg_6dc);
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printk(RAM_SPEW, "[6dc] <= %x\n",
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info->cached_training->reg_6dc);
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MCHBAR32(0x6dc) = info->cached_training->reg_6dc;
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} else
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set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11(info), 0,
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@ -3497,7 +3498,8 @@ static void set_2dxx_series(struct raminfo *info, int s3resume)
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set_2dx8_reg(info, 0x6e4, 1, 2 * info->fsb_frequency,
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frequency_11(info) / 2, 3500, 0, 0, 0);
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if (s3resume) {
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printk (BIOS_SPEW, "[6e8] <= %x\n", info->cached_training->reg_6e8);
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printk(RAM_SPEW, "[6e8] <= %x\n",
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info->cached_training->reg_6e8);
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MCHBAR32(0x6e8) = info->cached_training->reg_6e8;
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} else
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set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11(info), 0,
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@ -4026,19 +4028,19 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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int j;
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if (s3resume && info.cached_training) {
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restore_274265(&info);
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printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n",
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printk(RAM_DEBUG, "reg2ca9_bit0 = %x\n",
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info.cached_training->reg2ca9_bit0);
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for (i = 0; i < 2; i++)
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for (j = 0; j < 3; j++)
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printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n",
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printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n",
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i, j, info.cached_training->reg274265[i][j]);
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} else {
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set_274265(&info);
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printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n",
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printk(RAM_DEBUG, "reg2ca9_bit0 = %x\n",
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info.training.reg2ca9_bit0);
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for (i = 0; i < 2; i++)
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for (j = 0; j < 3; j++)
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printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n",
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printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n",
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i, j, info.training.reg274265[i][j]);
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}
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