From b331923c69fb15ca47bb89b1a08564532b83af22 Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@chromium.org>
Date: Thu, 28 Dec 2017 20:28:20 -0800
Subject: [PATCH] mainboard/google/zoombini: Add SoC acpi files to dsdt.asl

BUG=b:64395641
BRANCH=None
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.

Change-Id: I417a1c606e4968120414af57aa3b17d5c3b3cad0
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
---
 src/mainboard/google/zoombini/dsdt.asl | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/mainboard/google/zoombini/dsdt.asl b/src/mainboard/google/zoombini/dsdt.asl
index b1faad6ecc..c50a79ae42 100644
--- a/src/mainboard/google/zoombini/dsdt.asl
+++ b/src/mainboard/google/zoombini/dsdt.asl
@@ -24,14 +24,25 @@ DefinitionBlock(
 	0x20110725	// OEM revision
 )
 {
+	// Some generic macros
+	#include <soc/intel/cannonlake/acpi/platform.asl>
+
 	// global NVS and variables
 	#include <soc/intel/cannonlake/acpi/globalnvs.asl>
 
 	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/cannonlake/acpi/northbridge.asl>
+			#include <soc/intel/cannonlake/acpi/southbridge.asl>
+		}
 	}
 
 	#if IS_ENABLED(CONFIG_CHROMEOS)
 	// Chrome OS specific
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 	#endif
+
+	// Chipset specific sleep states
+	#include <soc/intel/cannonlake/acpi/sleepstates.asl>
 }