mb/intel/adlrvp_m: Enable CR50 TPM support over SPI
Add Kconfig options and enable TPM device in devicetree BUG=None TEST=Booted the image and checked the successful TPM communication in verstage,romstage & ramstage from coreboot logs. Signed-off-by: Thejaswani Puta thejaswani.putta@intel.com <thejaswani.putta@intel.com> Change-Id: Icaedf9f17e35e82c35cbabd6d2938c167e42e9e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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@ -22,6 +22,9 @@ config BOARD_SPECIFIC_OPTIONS
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select DRIVERS_I2C_MAX98373
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select FW_CONFIG if BOARD_INTEL_ADLRVP_M_EXT_EC
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select FW_CONFIG_SOURCE_CHROMEEC_CBI if BOARD_INTEL_ADLRVP_M_EXT_EC
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select MAINBOARD_HAS_TPM2 if BOARD_INTEL_ADLRVP_M_EXT_EC
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select MAINBOARD_HAS_SPI_TPM_CR50 if BOARD_INTEL_ADLRVP_M_EXT_EC
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select SPI_TPM if BOARD_INTEL_ADLRVP_M_EXT_EC
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config CHROMEOS
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select GBB_FLAG_FORCE_DEV_SWITCH_ON
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@ -91,11 +94,18 @@ endchoice
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config VBOOT
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select VBOOT_LID_SWITCH
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select VBOOT_MOCK_SECDATA
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select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC
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select EC_GOOGLE_CHROMEEC_SWITCHES if ADL_CHROME_EC
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select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_M_EXT_EC
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config UART_FOR_CONSOLE
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int
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default 0
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config DRIVER_TPM_SPI_BUS
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default 0x2 if BOARD_INTEL_ADLRVP_M_EXT_EC
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config TPM_TIS_ACPI_INTERRUPT
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int
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default 67 if BOARD_INTEL_ADLRVP_M_EXT_EC # GPE0_DW2_3 (GPP_E3)
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endif
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@ -6,6 +6,19 @@ fw_config
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end
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chip soc/intel/alderlake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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# This disables autonomous GPIO power management, otherwise
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# old cr50 FW only supports short pulses.
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register "gpio_override_pm" = "1"
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register "gpio_pm[COMM_0]" = "0"
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register "gpio_pm[COMM_1]" = "0"
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register "gpio_pm[COMM_2]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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register "gpio_pm[COMM_5]" = "0"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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@ -107,14 +120,14 @@ chip soc/intel/alderlake
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register "SerialIoGSpiMode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoPci,
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[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI1] = PchSerialIoPci,
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[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
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}"
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register "SerialIoGSpiCsMode" = "{
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[PchSerialIoIndexGSPI0] = 0,
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[PchSerialIoIndexGSPI1] = 0,
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[PchSerialIoIndexGSPI1] = 1,
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[PchSerialIoIndexGSPI2] = 0,
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[PchSerialIoIndexGSPI3] = 0,
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}"
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@ -141,6 +154,10 @@ chip soc/intel/alderlake
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# Intel Common SoC Config
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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.gspi[1] = {
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.speed_mhz = 1,
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.early_init = 1,
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},
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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},
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@ -353,6 +370,14 @@ chip soc/intel/alderlake
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device ref uart0 on end
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device ref gspi0 on end
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device ref p2sb on end
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device pci 1e.3 on
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chip drivers/spi/acpi
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register "hid" = "ACPI_DT_NAMESPACE_HID"
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register "compat_string" = ""google,cr50""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)"
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device spi 0 on end
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end
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end # GSPI1
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device ref hda on
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chip drivers/intel/soundwire
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device generic 0 on
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@ -99,6 +99,18 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1),
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/* H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT),
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/* TPM */
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/* F16 : GSPI1_CS0N */
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PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
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/* F11 : GSPI1_CLK */
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PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
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/* F13 : GSPI1_MISO */
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PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
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/* F12 : GSPI1_MOSI */
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PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
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};
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static const struct pad_config early_uart_gpio_table[] = {
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@ -159,7 +159,7 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
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/* S7 : SNDW4_DATA */
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PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2)
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PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
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};
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void variant_configure_gpio_pads(void)
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