util/superiotool/nuvoton.c: Add NCT6687D-W register definitions
Based on public NCT6686D hardware datasheet revision 0.5 which should be similar to NCT6687D. TEST=Dump NCT6687D, GPIO and EC registers on MSI PRO Z690-A WIFI DDR4 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I38db1de0f3d3b6de14bcb758afc9804c072c1895 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
This commit is contained in:
Michał Żygowski
parent
c28302fdda
commit
b33ee1da7d
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@ -5,6 +5,41 @@
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#define DEVICE_ID_REG 0x20 /* Super I/O ID (SID) / family */
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#define DEVICE_REV_REG 0x27 /* Super I/O revision ID (SRID) */
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static uint8_t regread(uint16_t port, uint8_t reg)
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{
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OUTB(reg, port);
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return INB(port + 1);
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}
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/* For Nuvoton EC space */
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static void set_page(uint16_t port, uint8_t page)
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{
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/*
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* INDEX reg can be written if PAGE reg is not 0xff
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* PAGE reg can be written if value or writing data is 0xff
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*/
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OUTB(0xff, port);
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OUTB(page, port);
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}
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static void dump_page_index_data(uint16_t iobase)
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{
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uint16_t i,j ;
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for (i = 0; i < 255; i++) {
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printf("Page %d:\n", i);
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for (j = 0; j < 256; j++) {
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if (j % 16 == 0)
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printf("\n%02x: ", j);
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/* PAGE must be selected before each data read */
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set_page(iobase, i);
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printf("%02x ", regread(iobase + 1, j));
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}
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printf("\n");
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}
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printf("\n");
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}
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static const struct superio_registers reg_table[] = {
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{0xfc, "WPCE775x / NPCE781x", {
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{NOLDN, NULL,
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@ -47,6 +82,73 @@ static const struct superio_registers reg_table[] = {
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{EOT}}},
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{0x1a, "WPCM450", {
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{EOT}}},
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{0xd592, "NCT6687D-W", {
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{NOLDN, "Global Configuration",
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{0x10,0x11,0x13,0x14,0x15,0x1a,0x1b,0x1d,0x1e,
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0x1f,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,
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0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2f,EOT},
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{0xff,0xff,0x00,0x00,0x00,0x00,0x10,0x00,0x00,
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0x00,0xd5,0x92,0x00,0x80,0x67,0x01,0x00,0x3e,
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0x00,0x03,0x0f,0x00,0x00,0x00,MISC,EOT}},
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{0x02, "Parallel Port",
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{0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
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{0x00,0x00,0x00,0x00,0x00,0x3f,EOT}},
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{0x02, "UART A",
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{0x30,0x60,0x61,0x70,0xf0,EOT},
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{0x00,0x00,0x00,0x00,0x00,EOT}},
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{0x03, "UART B, IR",
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{0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
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{0x00,0x00,0x00,0x00,0x00,0x00,EOT}},
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{0x05, "Keyboard Controller",
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{0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT},
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{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}},
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{0x06, "CIR",
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{0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,EOT},
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{0x00,0x00,0x00,0x00,0x08,0x09,0x32,0x00,EOT}},
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{0x07, "GPIO0-7",
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{0x30,0x60,0x61,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,
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0xe6,0xe7,0xe8,0xe9,0xeb,0xec,0xed,0xee,0xef,0xf0,
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0xf1,EOT},
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{0x00,0x00,0x00,0x00,NANA,NANA,NANA,NANA,NANA,NANA,
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NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
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0x01,EOT}},
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{0x08, "PORT80 UART",
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{0xe0,0xe1,0xe2,0xe3,0xe4,EOT},
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{0x80,0x00,0x00,0x10,0x00,EOT}},
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{0x09, "GPIO8-9, GPIO1-8 Alternate Function",
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{0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,
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0xe9,0xea,0xeb,0xec,0xed,0xee,0xef,EOT},
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{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}},
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{0x0a, "ACPI",
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{0x30,0x60,0x61,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe6,
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0xe7,0xe8,0xea,0xeb,0xec,0xee,0xf0,0xf1,0xf2,0xf3,
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0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,EOT},
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{0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
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0xef,0x80,0x2e,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
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0x0d,0x0d,0x01,0x00,0x04,0x00,0x00,0x00,0x04,EOT}},
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{0x0b, "EC",
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{0x30,0x60,0x61,0x70,0xe0,0xe3,0xe4,EOT},
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{0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}},
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{0x0c, "RTC",
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{0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,
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0xe9,0xea,0xeb,0xec,0xed,0xee,0xef,0xf0,EOT},
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{0x00,NANA,NANA,NANA,NANA,NANA,NANA,NANA,0x00,0x00,
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0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x80,EOT}},
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{0x0d, "Deep Sleep, Power Fault",
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{0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,
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0xf0,0xf1,0xf3,EOT},
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{0xa0,0x20,0x04,0x05,0x6e,0x00,0x00,0x00,0x88,0x77,
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0x70,0xaa,0x01,EOT}},
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{0x0e, "TACHIN/PWMOUT Assignment",
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{0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,
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0xea,0xeb,EOT},
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{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x00,0x00,EOT}},
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{0x0f, "Function Register",
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{0xe3,0xe4,0xe5,0xe8,0xe9,0xea,EOT},
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{0x80,0x01,0x00,0x00,0x00,0x00,EOT}},
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{EOT}}},
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{0xb472, "NCT6775F (A)", {
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{NOLDN, NULL,
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{0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,
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@ -682,6 +784,74 @@ static const struct superio_registers reg_table[] = {
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{EOT}
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};
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static void dump_nct6687d_gpios(uint16_t port)
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{
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uint8_t group, sel;
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const char *gpio_groups[] ={
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"0", "1", "2", "3", "4", "5", "6", "7", "8", "9",
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"Reserved", /* Does not exist */
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"EN0", /* Enhance 0 */
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"EN1", /* Enhance 1 */
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};
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/* Used by reg at 0xd offset to select which registers to reflect */
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const char *gpio_sel[] ={
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"GPIO Data",
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"GPIO Interrupt Enable",
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"GPIO Status",
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"GPIO I/O Control",
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"GPIO Inversion Control",
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"GPIO PP/OD Control",
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"GPIO Interrupt Type",
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"GPIO Output Data Reflection",
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"GPIO Internal Pull Down Control",
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"GPIO Reset Source Control",
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"Reserved",
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/* Below are valid only for GPIO Enhance Group 0 and 1 */
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"GPIO De-bounce Clock Option",
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"GPIO De-bounce Type 0",
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"GPIO De-bounce Type 1",
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"GPIO De-bounce Time Option 0",
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"GPIO De-bounce Time Option 1",
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};
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enter_conf_mode_winbond_fintek_ite_8787(port);
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regwrite(port, LDN_SEL, 0x07);
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printf("\nDumping GPIO configuration...\n\n");
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printf("%-35s", "GPIO Group");
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for (group = 0; group < ARRAY_SIZE(gpio_groups); group++) {
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if (group == 10)
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continue;
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printf("%-5s", gpio_groups[group]);
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}
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printf("\n");
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for (sel = 0; sel < ARRAY_SIZE(gpio_sel); sel++) {
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if (sel == 10)
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continue;
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printf("%-35s", gpio_sel[sel]);
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for (group = 0; group < ARRAY_SIZE(gpio_groups); group++) {
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if (group == 10)
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continue;
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/* Select GPIO group */
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regwrite(port, 0xf0, group);
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if (group < 11 && sel > 10)
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printf("XX ");
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else
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/* GPIO registers start at LDN 7 offset 0xe0 */
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printf("%02x ", regval(port, 0xe0 + sel));
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}
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printf("\n");
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}
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printf("\n");
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exit_conf_mode_winbond_fintek_ite_8787(port);
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}
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void probe_idregs_nuvoton(uint16_t port)
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{
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uint8_t sid, srid;
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@ -758,6 +928,17 @@ extra:
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for (i = 0; i < 10; i++)
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dump_data(iobase + 5, i);
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break;
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case 0xd590: /* NCT6687D-W */
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dump_nct6687d_gpios(port);
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/* One can use the APCI/BIOS register set, although the
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* resulting data is still the same when using software
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* register set.
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* printf("EC I/O base for ACPI/BIOS: 0x%x\n", iobase);
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* dump_page_index_data(iobase);
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*/
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printf("EC I/O base for software: 0x%x\n", iobase + 4);
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dump_page_index_data(iobase + 4);
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break;
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}
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}
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}
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