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soc/intel/apollolake: Rename `SOC_INTEL_GLK` symbol 

For consistency with other platforms, use `SOC_INTEL_GEMINILAKE`.

Change-Id: I06310e5a9bca6c9504f19a6c2fe9b26626f290d4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2020-09-07 13:18:10 +02:00 committed by Patrick Georgi
parent ee73594575
commit b36100faf4
17 changed files with 37 additions and 37 deletions
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2
src/mainboard/google/octopus/Kconfig
View File

@ -1,7 +1,7 @@
config BOARD_GOOGLE_BASEBOARD_OCTOPUS
def_bool n
select SOC_INTEL_GLK
select SOC_INTEL_GEMINILAKE
select BOARD_ROMSIZE_KB_16384
select DRIVERS_GENERIC_GPIO_KEYS
select DRIVERS_GENERIC_MAX98357A

2
src/mainboard/intel/glkrvp/Kconfig
View File

@ -1,7 +1,7 @@
config BOARD_INTEL_BASEBOARD_GLKRVP
def_bool n
select SOC_INTEL_GLK
select SOC_INTEL_GEMINILAKE
select BOARD_ROMSIZE_KB_16384
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID

18
src/soc/intel/apollolake/Kconfig
View File

@ -3,7 +3,7 @@ config SOC_INTEL_APOLLOLAKE
help
Intel Apollolake support
config SOC_INTEL_GLK
config SOC_INTEL_GEMINILAKE
bool
default n
select SOC_INTEL_APOLLOLAKE
@ -44,7 +44,7 @@ config CPU_SPECIFIC_OPTIONS
select GENERIC_GPIO_LIB
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
select HAVE_INTEL_FSP_REPO if !SOC_INTEL_GLK
select HAVE_INTEL_FSP_REPO if !SOC_INTEL_GEMINILAKE
select MRC_SETTINGS_PROTECT
select MRC_SETTINGS_VARIABLE_DATA
select NO_XIP_EARLY_STAGES
@ -96,8 +96,8 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_TSC
select TSC_MONOTONIC_TIMER
select PLATFORM_USES_FSP2_0
select UDK_2015_BINDING if !SOC_INTEL_GLK
select UDK_2017_BINDING if SOC_INTEL_GLK
select UDK_2015_BINDING if !SOC_INTEL_GEMINILAKE
select UDK_2017_BINDING if SOC_INTEL_GEMINILAKE
select SOC_INTEL_COMMON_RESET
select HAVE_CF9_RESET_PREPARE
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
@ -138,7 +138,7 @@ config DCACHE_RAM_BASE
config DCACHE_RAM_SIZE
hex
default 0x100000 if SOC_INTEL_GLK
default 0x100000 if SOC_INTEL_GEMINILAKE
default 0xc0000
help
The size of the cache-as-ram region required during bootblock
@ -183,7 +183,7 @@ config VERSTAGE_ADDR
The base address (in CAR) where verstage should be linked
config FSP_HEADER_PATH
default "src/vendorcode/intel/fsp/fsp2_0/glk" if SOC_INTEL_GLK
default "src/vendorcode/intel/fsp/fsp2_0/glk" if SOC_INTEL_GEMINILAKE
default "3rdparty/fsp/ApolloLakeFspBinPkg/Include/"
config FSP_FD_PATH
@ -293,7 +293,7 @@ config NHLT_RT5682
choice
prompt "Cache-as-ram implementation"
default CAR_CQOS if !SOC_INTEL_GLK
default CAR_CQOS if !SOC_INTEL_GEMINILAKE
default CAR_NEM
help
This option allows you to select how cache-as-ram (CAR) is set up.
@ -335,7 +335,7 @@ config CACHE_QOS_SIZE_PER_BIT
config L2_CACHE_SIZE
hex
default 0x400000 if SOC_INTEL_GLK
default 0x400000 if SOC_INTEL_GEMINILAKE
default 0x100000
config SMM_RESERVED_SIZE
@ -344,7 +344,7 @@ config SMM_RESERVED_SIZE
config IFD_CHIPSET
string
default "glk" if SOC_INTEL_GLK
default "glk" if SOC_INTEL_GEMINILAKE
default "aplk"
config CPU_BCLK_MHZ

8
src/soc/intel/apollolake/Makefile.inc
View File

@ -30,7 +30,7 @@ romstage-y += heci.c
romstage-y += i2c.c
romstage-y += uart.c
romstage-y += meminit.c
ifeq ($(CONFIG_SOC_INTEL_GLK),y)
ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y)
romstage-y += meminit_util_glk.c
else
romstage-y += meminit_util_apl.c
@ -90,7 +90,7 @@ verstage-y += pmutil.c
verstage-y += reset.c
verstage-y += spi.c
ifeq ($(CONFIG_SOC_INTEL_GLK),y)
ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y)
bootblock-y += gpio_glk.c
romstage-y += gpio_glk.c
smm-y += gpio_glk.c
@ -149,7 +149,7 @@ files_added:: $(IFWITOOL)
endif
# DSP firmware settings files.
ifeq ($(CONFIG_SOC_INTEL_GLK),y)
ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y)
NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/glk/nhlt-blobs
else
NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/apollolake/nhlt-blobs
@ -185,7 +185,7 @@ cbfs-files-$(CONFIG_NHLT_RT5682) += $(RT5682_RENDER_CAPTURE)
$(RT5682_RENDER_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(RT5682_RENDER_CAPTURE)
$(RT5682_RENDER_CAPTURE)-type := raw
ifeq ($(CONFIG_SOC_INTEL_GLK),y)
ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y)
# Gemini Lake B0 (706a1) only atm.
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-7a-*)
else

2
src/soc/intel/apollolake/acpi/pci_irqs.asl
View File

@ -15,7 +15,7 @@ Method(_PRT)
Package(){0x000FFFFF, 0, 0, CSE_INT},
Package(){0x0011FFFF, 0, 0, ISH_INT},
Package(){0x0012FFFF, 0, 0, SATA_INT},
#if CONFIG(SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GEMINILAKE)
Package(){0x000CFFFF, 0, 0, CNVI_INT},
Package(){0x0013FFFF, 0, 0, PIRQF_INT},
Package(){0x0013FFFF, 1, 0, PIRQF_INT},

2
src/soc/intel/apollolake/acpi/xhci.asl
View File

@ -21,7 +21,7 @@ Device (XHCI) {
/* Root Hub */
Name (_ADR, Zero)
#if CONFIG(SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GEMINILAKE)
#include "xhci_glk_ports.asl"
#else
#include "xhci_apl_ports.asl"

2
src/soc/intel/apollolake/bootblock/bootblock.c
View File

@ -23,7 +23,7 @@
#include <spi-generic.h>
static const struct pad_config tpm_spi_configs[] = {
#if CONFIG(SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GEMINILAKE)
PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */
#else
PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */

14
src/soc/intel/apollolake/chip.c
View File

@ -113,7 +113,7 @@ const char *soc_acpi_name(const struct device *dev)
case 6: return "HS07";
case 7: return "HS08";
case 8:
if (CONFIG(SOC_INTEL_GLK))
if (CONFIG(SOC_INTEL_GEMINILAKE))
return "HS09";
}
break;
@ -445,7 +445,7 @@ static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig)
case PCH_DEVFN_SMBUS:
silconfig->SmbusEnable = 0;
break;
#if !CONFIG(SOC_INTEL_GLK)
#if !CONFIG(SOC_INTEL_GEMINILAKE)
case SA_DEVFN_IPU:
silconfig->IpuEn = 0;
break;
@ -479,7 +479,7 @@ static void parse_devicetree(FSP_S_CONFIG *silconfig)
static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config
*cfg, FSP_S_CONFIG *silconfig)
{
#if !CONFIG(SOC_INTEL_GLK) /* GLK FSP does not have these fields in FspsUpd.h yet */
#if !CONFIG(SOC_INTEL_GEMINILAKE) /* GLK FSP does not have these fields in FspsUpd.h yet */
uint8_t port;
for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) {
@ -535,7 +535,7 @@ static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config
static void glk_fsp_silicon_init_params_cb(
struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig)
{
#if CONFIG(SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GEMINILAKE)
uint8_t port;
struct device *dev;
@ -665,7 +665,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
/* Disable monitor mwait since it is broken due to a hardware bug
* without a fix. Specific to Apollolake.
*/
if (!CONFIG(SOC_INTEL_GLK))
if (!CONFIG(SOC_INTEL_GEMINILAKE))
silconfig->MonitorMwaitEnable = 0;
silconfig->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
@ -681,7 +681,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable;
/* BIOS config lockdown Audio clk and power gate */
silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown;
if (CONFIG(SOC_INTEL_GLK))
if (CONFIG(SOC_INTEL_GEMINILAKE))
glk_fsp_silicon_init_params_cb(cfg, silconfig);
else
apl_fsp_silicon_init_params_cb(cfg, silconfig);
@ -813,7 +813,7 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase)
* Override GLK xhci clock gating register(XHCLKGTEN) to
* mitigate USB device suspend and resume failure.
*/
if (CONFIG(SOC_INTEL_GLK)) {
if (CONFIG(SOC_INTEL_GEMINILAKE)) {
uint32_t *cfg;
const struct resource *res;
uint32_t reg;

2
src/soc/intel/apollolake/cpu.c
View File

@ -30,7 +30,7 @@
#include <soc/pm.h>
static const struct reg_script core_msr_script[] = {
#if !CONFIG(SOC_INTEL_GLK)
#if !CONFIG(SOC_INTEL_GEMINILAKE)
/* Enable C-state and IO/MWAIT redirect */
REG_MSR_WRITE(MSR_PKG_CST_CONFIG_CONTROL,
(PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK

2
src/soc/intel/apollolake/include/soc/gpio.h
View File

@ -3,7 +3,7 @@
#ifndef _SOC_APL_GPIO_H_
#define _SOC_APL_GPIO_H_
#if CONFIG(SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GEMINILAKE)
#include <soc/gpio_glk.h>
#else
#include <soc/gpio_apl.h>

2
src/soc/intel/apollolake/include/soc/pcr_ids.h
View File

@ -6,7 +6,7 @@
/*
* Port ids.
*/
#if CONFIG(SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GEMINILAKE)
#define PID_GPIO_AUDIO 0xC9
#define PID_GPIO_SCC 0xC8
#else

2
src/soc/intel/apollolake/include/soc/pm.h
View File

@ -177,7 +177,7 @@
#define GPE0_DWX_MASK 0xf
#define GPE0_DW_SHIFT(x) (4 + 4*(x))
#if CONFIG(SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GEMINILAKE)
#define PMC_GPE_AUDIO_31_0 9
#define PMC_GPE_N_95_64 8
#define PMC_GPE_N_63_32 7

2
src/soc/intel/apollolake/lpc.c
View File

@ -28,7 +28,7 @@ const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
}
static const struct pad_config lpc_gpios[] = {
#if CONFIG(SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GEMINILAKE)
#if !CONFIG(SOC_ESPI)
PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1), /* LPC_ILB_SERIRQ */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, NONE, DEEP, NF1, HIZCRx1,

2
src/soc/intel/apollolake/meminit.c
View File

@ -152,7 +152,7 @@ static const struct fsp_speed_profiles glk_profile = {
static const struct fsp_speed_profiles *get_fsp_profile(void)
{
if (CONFIG(SOC_INTEL_GLK))
if (CONFIG(SOC_INTEL_GEMINILAKE))
return &glk_profile;
else
return &apl_profile;

8
src/soc/intel/apollolake/romstage.c
View File

@ -107,7 +107,7 @@ static bool punit_init(void)
PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER |
PUINT_THERMAL_DEVICE_IRQ_LOCK;
if (!CONFIG(SOC_INTEL_GLK)) {
if (!CONFIG(SOC_INTEL_GEMINILAKE)) {
data = MCHBAR32(0x7818);
data &= 0xFFFFE01F;
data |= 0x20 | 0x200;
@ -231,7 +231,7 @@ static void check_full_retrain(const FSPM_UPD *mupd)
static void soc_memory_init_params(FSPM_UPD *mupd)
{
#if CONFIG(SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GEMINILAKE)
/* Only for GLK */
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
@ -258,7 +258,7 @@ static void parse_devicetree_setting(FSPM_UPD *m_upd)
{
DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_NPK);
#if CONFIG(SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GEMINILAKE)
m_upd->FspmConfig.TraceHubEn = is_dev_enabled(dev);
#else
m_upd->FspmConfig.NpkEn = is_dev_enabled(dev);
@ -271,7 +271,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
fill_console_params(mupd);
if (CONFIG(SOC_INTEL_GLK))
if (CONFIG(SOC_INTEL_GEMINILAKE))
soc_memory_init_params(mupd);
mainboard_memory_init_params(mupd);

2
src/soc/intel/apollolake/uart.c
View File

@ -13,7 +13,7 @@
/* UART pad configuration. Support RXD and TXD for now. */
const struct uart_gpio_pad_config uart_gpio_pads[] = {
#if CONFIG(SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GEMINILAKE)
{
.console_index = 0,
.gpios = {

2
src/soc/intel/apollolake/xhci.c
View File

@ -3,7 +3,7 @@
#include <intelblocks/xhci.h>
#define XHCI_USB2_PORT_STATUS_REG 0x480
#if CONFIG(SOC_INTEL_GLK)
#if CONFIG(SOC_INTEL_GEMINILAKE)
#define XHCI_USB3_PORT_STATUS_REG 0x510
#define XHCI_USB2_PORT_NUM 9
#else