GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

rockchip: Correct and standardize clock divisor range assertions 

Some of the asserts for valid clock divisor ranges were off by one. This
patch corrects them and writes them all in a consistent way.

BRANCH=None
BUG=None
TEST=Booted Kevin.

Change-Id: I81749408a40822100797f1734f3b88987d12d8d5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e09cdfde26700496aaa1fc41489f63a355e8a89d
Original-Change-Id: I429edb99e2d5ff2302d9750e6569b3d21f5686fa
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/381574
Original-Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/16704
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Julius Werner 2016-09-06 14:09:16 -07:00 committed by Patrick Georgi
parent aa58a9eebf
commit b37c8c065c
2 changed files with 26 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
src/soc/rockchip/rk3288/clock.c
View File

@ -272,14 +272,14 @@ void rkclk_init(void)
* set up dependent divisors for PCLK/HCLK and ACLK clocks.
*/
aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
PD_BUS_ACLK_HZ && (hclk_div <= 0x3) && (hclk_div != 0x2));
pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
PD_BUS_ACLK_HZ && pclk_div < 0x7);
PD_BUS_ACLK_HZ && pclk_div <= 0x7);
write32(&cru_ptr->cru_clksel_con[1], RK_SETBITS(PD_BUS_SEL_GPLL) |
RK_CLRSETBITS(PD_BUS_PCLK_DIV_MSK,
@ -295,15 +295,15 @@ void rkclk_init(void)
* set up dependent divisors for PCLK/HCLK and ACLK clocks.
*/
aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ);
assert((1 << hclk_div) * PERI_HCLK_HZ ==
PERI_ACLK_HZ && (hclk_div < 0x4));
PERI_ACLK_HZ && (hclk_div <= 0x2));
pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ);
assert((1 << pclk_div) * PERI_PCLK_HZ ==
PERI_ACLK_HZ && (pclk_div < 0x4));
PERI_ACLK_HZ && (pclk_div <= 0x3));
write32(&cru_ptr->cru_clksel_con[10], RK_SETBITS(PERI_SEL_GPLL) |
RK_CLRSETBITS(PERI_PCLK_DIV_MSK,
@ -429,7 +429,7 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz)
{
int src_clk_div = GPLL_HZ / hz;
assert((src_clk_div - 1 < 127) && (src_clk_div * hz == GPLL_HZ));
assert((src_clk_div - 1 <= 127) && (src_clk_div * hz == GPLL_HZ));
switch (bus) { /*select gpll as spi src clk, and set div*/
case 0:
@ -487,7 +487,7 @@ void rkclk_configure_crypto(unsigned int hz)
{
u32 div = PD_BUS_ACLK_HZ / hz;
assert((div - 1 < 4) && (div * hz == PD_BUS_ACLK_HZ));
assert((div - 1 <= 3) && (div * hz == PD_BUS_ACLK_HZ));
assert(hz <= 150*MHz); /* Suggested max in TRM. */
write32(&cru_ptr->cru_clksel_con[26],
RK_CLRSETBITS(0x3 << 6, (div - 1) << 6));
@ -499,7 +499,7 @@ void rkclk_configure_tsadc(unsigned int hz)
u32 src_clk = 32 * KHz; /* tsadc source clock is 32KHz*/
div = src_clk / hz;
assert((div - 1 < 64) && (div * hz == 32 * KHz));
assert((div - 1 <= 63) && (div * hz == 32 * KHz));
write32(&cru_ptr->cru_clksel_con[2],
RK_CLRSETBITS(0x3f << 0, (div - 1) << 0));
}
@ -604,7 +604,7 @@ void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz)
/* vop aclk source clk: cpll */
div = CPLL_HZ / aclk_hz;
assert((div - 1 < 64) && (div * aclk_hz == CPLL_HZ));
assert((div - 1 <= 63) && (div * aclk_hz == CPLL_HZ));
switch (vop_id) {
case 0:

32
src/soc/rockchip/rk3399/clock.c
View File

@ -402,7 +402,7 @@ void rkclk_init(void)
/* configure pmu pclk */
pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
assert((pclk_div + 1) * PMU_PCLK_HZ == PPLL_HZ && pclk_div < 0x1f);
assert((pclk_div + 1) * PMU_PCLK_HZ == PPLL_HZ && pclk_div <= 0x1f);
write32(&pmucru_ptr->pmucru_clksel[0],
RK_CLRSETBITS(PMU_PCLK_DIV_CON_MASK << PMU_PCLK_DIV_CON_SHIFT,
pclk_div << PMU_PCLK_DIV_CON_SHIFT));
@ -420,15 +420,15 @@ void rkclk_init(void)
/* configure perihp aclk, hclk, pclk */
aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
PERIHP_ACLK_HZ && (hclk_div < 0x4));
PERIHP_ACLK_HZ && (hclk_div <= 0x3));
pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
PERIHP_ACLK_HZ && (pclk_div < 0x7));
PERIHP_ACLK_HZ && (pclk_div <= 0x7));
write32(&cru_ptr->clksel_con[14],
RK_CLRSETBITS(PCLK_PERIHP_DIV_CON_MASK <<
@ -447,15 +447,15 @@ void rkclk_init(void)
/* configure perilp0 aclk, hclk, pclk */
aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
PERILP0_ACLK_HZ && (hclk_div < 0x4));
PERILP0_ACLK_HZ && (hclk_div <= 0x3));
pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
PERILP0_ACLK_HZ && (pclk_div < 0x7));
PERILP0_ACLK_HZ && (pclk_div <= 0x7));
write32(&cru_ptr->clksel_con[23],
RK_CLRSETBITS(PCLK_PERILP0_DIV_CON_MASK <<
@ -475,11 +475,11 @@ void rkclk_init(void)
/* perilp1 hclk select gpll as source */
hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
GPLL_HZ && (hclk_div < 0x1f));
GPLL_HZ && (hclk_div <= 0x1f));
pclk_div = PERILP1_HCLK_HZ / PERILP1_PCLK_HZ - 1;
assert((pclk_div + 1) * PERILP1_PCLK_HZ ==
PERILP1_HCLK_HZ && (pclk_div < 0x7));
PERILP1_HCLK_HZ && (pclk_div <= 0x7));
write32(&cru_ptr->clksel_con[25],
RK_CLRSETBITS(PCLK_PERILP1_DIV_CON_MASK <<
@ -590,7 +590,7 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz)
/* spi3 src clock from ppll, while spi0,1,2,4,5 src clock from gpll */
pll = (bus == 3) ? PPLL_HZ : GPLL_HZ;
src_clk_div = pll / hz;
assert((src_clk_div - 1 < 127) && (src_clk_div * hz == pll));
assert((src_clk_div - 1 <= 127) && (src_clk_div * hz == pll));
switch (bus) {
case 0:
@ -646,7 +646,7 @@ static void rkclk_configure_i2c(unsigned int bus, unsigned int hz)
/* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
pll = (bus == 0 || bus == 4 || bus == 8) ? PPLL_HZ : GPLL_HZ;
src_clk_div = pll / hz;
assert((src_clk_div - 1 < 127) && (src_clk_div * hz == pll));
assert((src_clk_div - 1 <= 127) && (src_clk_div * hz == pll));
switch (bus) {
case 0:
@ -749,7 +749,7 @@ void rkclk_configure_saradc(unsigned int hz)
/* saradc src clk from 24MHz */
src_clk_div = 24 * MHz / hz;
assert((src_clk_div - 1 < 255) && (src_clk_div * hz == 24 * MHz));
assert((src_clk_div - 1 <= 255) && (src_clk_div * hz == 24 * MHz));
write32(&cru_ptr->clksel_con[26],
RK_CLRSETBITS(CLK_SARADC_DIV_CON_MASK <<
@ -765,7 +765,7 @@ void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz)
/* vop aclk source clk: cpll */
div = CPLL_HZ / aclk_hz;
assert((div - 1 < 32) && (div * aclk_hz == CPLL_HZ));
assert((div - 1 <= 31) && (div * aclk_hz == CPLL_HZ));
write32(reg_addr, RK_CLRSETBITS(
ACLK_VOP_PLL_SEL_MASK << ACLK_VOP_PLL_SEL_SHIFT |
@ -803,7 +803,7 @@ void rkclk_configure_tsadc(unsigned int hz)
/* use 24M as src clock */
src_clk_div = OSC_HZ / hz;
assert((src_clk_div - 1 < 1024) && (src_clk_div * hz == OSC_HZ));
assert((src_clk_div - 1 <= 1023) && (src_clk_div * hz == OSC_HZ));
write32(&cru_ptr->clksel_con[27], RK_CLRSETBITS(
CLK_TSADC_DIV_CON_MASK << CLK_TSADC_DIV_CON_SHIFT |
@ -820,7 +820,7 @@ void rkclk_configure_emmc(void)
/* Select aclk_emmc source from GPLL */
src_clk_div = GPLL_HZ / aclk_emmc;
assert((src_clk_div - 1 < 31) && (src_clk_div * aclk_emmc == GPLL_HZ));
assert((src_clk_div - 1 <= 31) && (src_clk_div * aclk_emmc == GPLL_HZ));
write32(&cru_ptr->clksel_con[21],
RK_CLRSETBITS(ACLK_EMMC_PLL_SEL_MASK <<
@ -832,7 +832,7 @@ void rkclk_configure_emmc(void)
/* Select clk_emmc source from GPLL too */
src_clk_div = GPLL_HZ / clk_emmc;
assert((src_clk_div - 1 < 127) && (src_clk_div * clk_emmc == GPLL_HZ));
assert((src_clk_div - 1 <= 127) && (src_clk_div * clk_emmc == GPLL_HZ));
write32(&cru_ptr->clksel_con[22],
RK_CLRSETBITS(CLK_EMMC_PLL_MASK << CLK_EMMC_PLL_SHIFT |